radv: add gfx9 depth/stencil surface support.

This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8d04be7295e6d3620aae3a6210593b41f80a9110..e7b8c41c67dc65ddc24b9db037f3b42321372a60 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -961,20 +961,45 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
        }
 
        radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
-       radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
-
-       radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
-       radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
-       radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
-       radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
-       radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
-       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
-       radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
-       radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
-       radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
-       radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
-
-       radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
+
+       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
+               radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
+               radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
+               radeon_emit(cmd_buffer->cs, ds->db_depth_size);
+
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
+               radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
+               radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);  /* DB_Z_READ_BASE_HI */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
+               radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
+
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
+               radeon_emit(cmd_buffer->cs, ds->db_z_info2);
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
+       } else {
+               radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
+
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
+               radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
+               radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
+               radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
+               radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
+               radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
+               radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
+
+               radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
+       }
+
        radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
                               ds->pa_su_poly_offset_db_fmt_cntl);
 }

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8defb736b2c50c56ebe615828f960c653ca12a4e..ca42ab8e0e10995455ae8929ed51c7760cc29f52 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2913,7 +2913,39 @@ radv_initialise_ds_surface(struct radv_device *device,
        va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
        s_offs = z_offs = va;
 
-       {
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
+               assert(iview->image->surface.u.gfx9.surf_offset == 0);
+               s_offs += iview->image->surface.u.gfx9.stencil_offset;
+
+               ds->db_z_info = S_028038_FORMAT(format) |
+                       S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
+                       S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
+                       S_028038_MAXMIP(iview->image->info.levels - 1);
+               ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
+                       S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
+
+               ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
+               ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
+               ds->db_depth_view |= S_028008_MIPID(level);
+
+               ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
+                       S_02801C_Y_MAX(iview->image->info.height - 1);
+
+               /* Only use HTILE for the first level. */
+               if (iview->image->surface.htile_size && !level) {
+                       ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
+
+                       if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
+                               /* Use all of the htile_buffer for depth if there's no stencil. */
+                               ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
+                       va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
+                               iview->image->htile_offset;
+                       ds->db_htile_data_base = va >> 8;
+                       ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
+                               S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
+                               S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
+               }
+       } else {
                const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
 
                if (stencil_only)

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 59b592e42a5efc058a9d107606ed6b79495ca960..e1b9a29cee1a91c3f045de5dd0aa4348d886aa1a 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1366,6 +1366,8 @@ struct radv_ds_buffer_info {
        uint32_t db_depth_slice;
        uint32_t db_htile_surface;
        uint32_t pa_su_poly_offset_db_fmt_cntl;
+       uint32_t db_z_info2;
+       uint32_t db_stencil_info2;
        float offset_scale;
 };