gallium/radeon/winsyses: reduce the number of pb_cache buckets

Small buffers are now handled via the slabs code, so separate buckets in
pb_cache have become redundant.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/auxiliary/pipebuffer/pb_cache.h b/src/gallium/auxiliary/pipebuffer/pb_cache.h
index aa83cc8b38ced6ad768c38aab7c6b5f6af7787db..7000fcd1c5a8ffcc8bbb3b363ad77f7ac064fb90 100644 (file)
--- a/src/gallium/auxiliary/pipebuffer/pb_cache.h
+++ b/src/gallium/auxiliary/pipebuffer/pb_cache.h
@@ -50,7 +50,7 @@ struct pb_cache
    /* The cache is divided into buckets for minimizing cache misses.
     * The driver controls which buffer goes into which bucket.
     */
-   struct list_head buckets[8];
+   struct list_head buckets[4];
 
    pipe_mutex mutex;
    uint64_t cache_size;

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index c13dc2b0e90a63b9a0476d85f76f1846d622e3f9..e8d2c006f36e526c1c6cab6604cbfeda8da5ae75 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -741,12 +741,10 @@ no_slab:
 
    /* Determine the pb_cache bucket for minimizing pb_cache misses. */
    pb_cache_bucket = 0;
-   if (size <= 4096) /* small buffers */
-      pb_cache_bucket += 1;
    if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */
-      pb_cache_bucket += 2;
+      pb_cache_bucket += 1;
    if (flags == RADEON_FLAG_GTT_WC) /* WC */
-      pb_cache_bucket += 4;
+      pb_cache_bucket += 2;
    assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets));
 
    /* Get a buffer from the cache. */

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 3af01f82fb6ed3a986eaba1a92855b22a3858b5f..5818006cc2acf3c8f3a5205ee614e6871987324b 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -1014,12 +1014,10 @@ no_slab:
 
     /* Determine the pb_cache bucket for minimizing pb_cache misses. */
     pb_cache_bucket = 0;
-    if (size <= 4096) /* small buffers */
-       pb_cache_bucket += 1;
     if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */
-       pb_cache_bucket += 2;
+       pb_cache_bucket += 1;
     if (flags == RADEON_FLAG_GTT_WC) /* WC */
-       pb_cache_bucket += 4;
+       pb_cache_bucket += 2;
     assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets));
 
     bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment,