radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE

Two more little piglits.

NOTE: This is a candidate for the 9.1 branch.

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 388f6df0518735d116d257588a9d82f418c300b8..c5b33f721a4f85b0d8ec92072c20d1020c990e64 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -140,7 +140,6 @@ struct r600_context {
        unsigned                        pa_sc_line_stipple;
        unsigned                        pa_su_sc_mode_cntl;
        unsigned                        pa_cl_clip_cntl;
-       unsigned                        pa_cl_vs_out_cntl;
        /* for saving when using blitter */
        struct pipe_stencil_ref         stencil_ref;
        struct si_pipe_shader_selector  *ps_shader;

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index bea2895bf0c949eb496d61914fbf302b74dc71aa..e6ed5459ceadd80ed56ce8922df89ddbd79114a4 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -612,7 +612,9 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
                        /* Select the correct target */
                        switch(d->Semantic.Name) {
                        case TGSI_SEMANTIC_PSIZE:
-                               target = V_008DFC_SQ_EXP_POS;
+                               shader->vs_out_misc_write = 1;
+                               shader->vs_out_point_size = 1;
+                               target = V_008DFC_SQ_EXP_POS + 1;
                                break;
                        case TGSI_SEMANTIC_POSITION:
                                if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 0fbd601ad34f516426f846c48fb6a4a497256c5e..667f2c339852cba9770390a0bb0709cbf49c3dce 100644 (file)
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -110,6 +110,8 @@ struct si_shader {
        bool                    uses_kill;
        bool                    uses_instanceid;
        bool                    fs_write_all;
+       bool                    vs_out_misc_write;
+       bool                    vs_out_point_size;
        unsigned                nr_cbufs;
 };
 

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index ed95b1d8d8979f10cc5659a20cbda17c4797ad6e..6d072ef725aeead024a256206c5d6168772d4f99 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -412,9 +412,6 @@ static void *si_create_rs_state(struct pipe_context *ctx,
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
                S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
-       rs->pa_cl_vs_out_cntl =
-               S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
-               S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
 
        clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 
@@ -485,7 +482,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
        rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
        rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
        rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
-       rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
 
        si_pm4_bind_state(rctx, rasterizer, rs);
        si_update_fb_rs_state(rctx);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8d169079f4b269508f85652b9b7022b437380db6..a9ecc64afa48fc71dc769f973c372938b7454216 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -55,8 +55,13 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
         * takes care of adding a dummy export.
         */
        for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
-               if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
+               switch (shader->shader.output[i].name) {
+               case TGSI_SEMANTIC_POSITION:
+               case TGSI_SEMANTIC_PSIZE:
+                       break;
+               default:
                        nparams++;
+               }
        }
        if (nparams < 1)
                nparams = 1;
@@ -66,7 +71,9 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
 
        si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
                       S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
-                      S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
+                      S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
+                                                  V_02870C_SPI_SHADER_4COMP :
+                                                  V_02870C_SPI_SHADER_NONE) |
                       S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
                       S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
 
@@ -261,6 +268,7 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
                               const struct pipe_draw_info *info)
 {
        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+       struct si_shader *vs = &rctx->vs_shader->current->shader;
        unsigned prim = si_conv_pipe_prim(info->mode);
        unsigned ls_mask = 0;
 
@@ -297,7 +305,8 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
                si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
         }
        si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
-                      prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
+                      S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
+                      S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write)
                       /*| (rctx->rasterizer->clip_plane_enable &
                       rctx->vs_shader->shader.clip_dist_write)*/);
        si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl