amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated...

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 8506a45ae907632d39c14a8ad4423fcc9788ba2e..d2d6d94698e15976de74a8accfb5d67baadc606b 100644 (file)
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -906,6 +906,8 @@ typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
     UINT_32 macroWidth;         ///< Macro width in pixels, actually squared cache shape
     UINT_32 macroHeight;        ///< Macro height in pixels
     UINT_64 sliceSize;          ///< Slice size, in bytes.
+    BOOL_32 sliceInterleaved;   ///< Flag to indicate if different slice's htile is interleaved
+                                ///  Compute engine clear can't be used if htile is interleaved
 } ADDR_COMPUTE_HTILE_INFO_OUTPUT;
 
 /**

diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index fb33145f88df283483c54f62fd8c7fa7239994ad..809bca23914bc331f887dc5a41c1f740d8b1f193 100644 (file)
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -1295,6 +1295,22 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
                                          &pOut->macroHeight,
                                          &pOut->sliceSize,
                                          &pOut->baseAlign);
+
+            if (pIn->flags.tcCompatible && (pIn->numSlices > 1))
+            {
+                pOut->sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
+
+                const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
+
+                if ((pOut->sliceSize % align) == 0)
+                {
+                    pOut->sliceInterleaved = FALSE;
+                }
+                else
+                {
+                    pOut->sliceInterleaved = TRUE;
+                }
+            }
         }
     }