radv: initialize HTILE for separate depth/stencil aspects

It either clears the whole HTILE buffer or part of it depending
on the HTILE mask parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 53c562b5df65f56993c52fffd1ece4d265a95fef..abe3778986381c5892bee4e1529023679db68080 100644 (file)
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -221,7 +221,7 @@ uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
                        struct radv_image *image,
                        const VkImageSubresourceRange *range, uint32_t value);
 uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
-                         struct radv_image *image,
+                         const struct radv_image *image,
                          const VkImageSubresourceRange *range, uint32_t value);
 
 /**

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 04f0b8a3f9d2bb2fe0807dff9485317a89babcd8..f57cbba68feb89d5253b86b2e17983bdc6755fcc 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1084,10 +1084,8 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
        VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
        VkImageAspectFlags aspects = clear_att->aspectMask;
        uint32_t clear_word, flush_bits;
-       uint32_t htile_mask;
 
        clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value);
-       htile_mask = radv_get_htile_mask(iview->image, aspects);
 
        if (pre_flush) {
                cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
@@ -1095,18 +1093,15 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
                *pre_flush |= cmd_buffer->state.flush_bits;
        }
 
-       if (htile_mask == UINT_MAX) {
-               /* Clear the whole HTILE buffer. */
-               flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
-                                             iview->image->offset + iview->image->htile_offset,
-                                             iview->image->planes[0].surface.htile_size, clear_word);
-       } else {
-               /* Only clear depth or stencil bytes in the HTILE buffer. */
-               flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo,
-                                             iview->image->offset + iview->image->htile_offset,
-                                             iview->image->planes[0].surface.htile_size, clear_word,
-                                             htile_mask);
-       }
+       struct VkImageSubresourceRange range = {
+               .aspectMask = aspects,
+               .baseMipLevel = 0,
+               .levelCount = VK_REMAINING_MIP_LEVELS,
+               .baseArrayLayer = 0,
+               .layerCount = VK_REMAINING_ARRAY_LAYERS,
+       };
+
+       flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word);
 
        if (iview->image->planes[0].surface.has_stencil &&
            !(aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
@@ -1530,15 +1525,30 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 }
 
 uint32_t
-radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
-                const VkImageSubresourceRange *range, uint32_t value)
+radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
+                const struct radv_image *image,
+                const VkImageSubresourceRange *range,
+                uint32_t value)
 {
        unsigned layer_count = radv_get_layerCount(image, range);
        uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
        uint64_t offset = image->offset + image->htile_offset +
                          image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
+       uint32_t htile_mask, flush_bits;
 
-       return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
+       htile_mask = radv_get_htile_mask(image, range->aspectMask);
+
+       if (htile_mask == UINT_MAX) {
+               /* Clear the whole HTILE buffer. */
+               flush_bits = radv_fill_buffer(cmd_buffer, image->bo, offset,
+                                             size, value);
+       } else {
+               /* Only clear depth or stencil bytes in the HTILE buffer. */
+               flush_bits = clear_htile_mask(cmd_buffer, image->bo, offset,
+                                             size, value, htile_mask);
+       }
+
+       return flush_bits;
 }
 
 enum {

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index f3bdfdbbd11bc8cbd47508ab507906adb6b04ad2..d1d69cbd8ae1b9a03386e51576aaa83544313069 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -1043,7 +1043,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
        if (radv_image_has_htile(dst_image)) {
                if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
                        VkImageSubresourceRange range = {};
-                       range.aspectMask = aspects;
+                       range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
                        range.baseMipLevel = dst_iview->base_mip;
                        range.levelCount = 1;
                        range.baseArrayLayer = dst_iview->base_layer;