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amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile
authorMarek Olšák <marek.olsak@amd.com>
Sat, 2 May 2020 13:19:18 +0000 (09:19 -0400)
committerMarge Bot <eric+marge@anholt.net>
Thu, 7 May 2020 20:13:41 +0000 (20:13 +0000)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>

src/amd/common/ac_surface.c patch | blob | history
src/amd/common/ac_surface.h patch | blob | history
src/amd/vulkan/radv_device.c patch | blob | history
src/amd/vulkan/radv_image.c patch | blob | history
src/gallium/drivers/radeonsi/si_descriptors.c patch | blob | history
src/gallium/drivers/radeonsi/si_state.c patch | blob | history
src/gallium/drivers/radeonsi/si_texture.c patch | blob | history

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1ad9bfbb5fb6c456dc14c2a54b086cc1fc3a10cd..6b00eea8221954de1718384daf099d8f6754ab3f 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1178,8 +1178,11 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
                hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
                hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 
                hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
                hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 
-               hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
-               hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
+               assert(in->flags.metaPipeUnaligned == 0);
+               assert(in->flags.metaRbUnaligned == 0);
+
+               hin.hTileFlags.pipeAligned = 1;
+               hin.hTileFlags.rbAligned = 1;
                hin.depthFlags = in->flags;
                hin.swizzleMode = in->swizzleMode;
                hin.unalignedWidth = in->width;
                hin.depthFlags = in->flags;
                hin.swizzleMode = in->swizzleMode;
                hin.unalignedWidth = in->width;
@@ -1192,8 +1195,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
                if (ret != ADDR_OK)
                        return ret;
 
                if (ret != ADDR_OK)
                        return ret;
 
-               surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
-               surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
                surf->htile_size = hout.htileBytes;
                surf->htile_slice_size = hout.sliceSize;
                surf->htile_alignment = hout.baseAlign;
                surf->htile_size = hout.htileBytes;
                surf->htile_slice_size = hout.sliceSize;
                surf->htile_alignment = hout.baseAlign;
@@ -1604,7 +1605,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
        else
                AddrSurfInfoIn.numSlices = config->info.array_size;
 
        else
                AddrSurfInfoIn.numSlices = config->info.array_size;
 
-       /* This is propagated to HTILE/DCC. */
+       /* This is propagated to DCC. It must be 0 for HTILE and CMASK. */
        AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
        AddrSurfInfoIn.flags.metaRbUnaligned = 0;
 
        AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
        AddrSurfInfoIn.flags.metaRbUnaligned = 0;
 
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 5a1381980f2782ee6e176d86f5b06b18a291d585..2f7b928f95f378ee63c2f6de29bce0acb9117305 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -150,7 +150,6 @@ struct gfx9_surf_layout {
     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 
     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
     struct gfx9_surf_flags      stencil; /* added to surf_size, use stencil_offset */
 
     struct gfx9_surf_meta_flags dcc;   /* metadata of color */
-    struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
     uint16_t                    surf_pitch; /* in blocks */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
     uint16_t                    surf_pitch; /* in blocks */
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 883d7d49efc48a385332c8abc2ea65ddbe143b21..d4b78ef06df985f8f419288aa25e55fc4b5c1c30 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -6810,10 +6810,10 @@ radv_initialise_ds_surface(struct radv_device *device,
                                iview->image->htile_offset;
                        ds->db_htile_data_base = va >> 8;
                        ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
                                iview->image->htile_offset;
                        ds->db_htile_data_base = va >> 8;
                        ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
-                               S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
+                               S_028ABC_PIPE_ALIGNED(1);
 
                        if (device->physical_device->rad_info.chip_class == GFX9) {
 
                        if (device->physical_device->rad_info.chip_class == GFX9) {
-                               ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
+                               ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
                        }
                }
        } else {
                        }
                }
        } else {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 1387715892451d1b53f68f2cd2f648c675db6a5d..12cf6fb6eb71a38cb59f29c557b198ae0a53f1c2 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -609,12 +609,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                            C_00A018_META_PIPE_ALIGNED;
 
                if (meta_va) {
                            C_00A018_META_PIPE_ALIGNED;
 
                if (meta_va) {
-                       struct gfx9_surf_meta_flags meta;
+                       struct gfx9_surf_meta_flags meta = {
+                               .rb_aligned = 1,
+                               .pipe_aligned = 1,
+                       };
 
                        if (image->dcc_offset)
                                meta = plane->surface.u.gfx9.dcc;
 
                        if (image->dcc_offset)
                                meta = plane->surface.u.gfx9.dcc;
-                       else
-                               meta = plane->surface.u.gfx9.htile;
 
                        state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
                                    S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
 
                        state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
                                    S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
@@ -637,12 +638,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
                            C_008F24_META_PIPE_ALIGNED &
                            C_008F24_META_RB_ALIGNED;
                if (meta_va) {
                            C_008F24_META_PIPE_ALIGNED &
                            C_008F24_META_RB_ALIGNED;
                if (meta_va) {
-                       struct gfx9_surf_meta_flags meta;
+                       struct gfx9_surf_meta_flags meta = {
+                               .rb_aligned = 1,
+                               .pipe_aligned = 1,
+                       };
 
                        if (image->dcc_offset)
                                meta = plane->surface.u.gfx9.dcc;
 
                        if (image->dcc_offset)
                                meta = plane->surface.u.gfx9.dcc;
-                       else
-                               meta = plane->surface.u.gfx9.htile;
 
                        state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
                                    S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
 
                        state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
                                    S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 95d77b3347c4777774c8b6773406f0717766b461..572523992ccb080b583a443940b1d3e0860e94e1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -349,12 +349,13 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
       state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
 
       if (meta_va) {
       state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
 
       if (meta_va) {
-         struct gfx9_surf_meta_flags meta;
+         struct gfx9_surf_meta_flags meta = {
+            .rb_aligned = 1,
+            .pipe_aligned = 1,
+         };
 
          if (tex->surface.dcc_offset)
             meta = tex->surface.u.gfx9.dcc;
 
          if (tex->surface.dcc_offset)
             meta = tex->surface.u.gfx9.dcc;
-         else
-            meta = tex->surface.u.gfx9.htile;
 
          state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
                      S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
 
          state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
                      S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
@@ -376,12 +377,13 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
       state[5] &=
          C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
       if (meta_va) {
       state[5] &=
          C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
       if (meta_va) {
-         struct gfx9_surf_meta_flags meta;
+         struct gfx9_surf_meta_flags meta = {
+            .rb_aligned = 1,
+            .pipe_aligned = 1,
+         };
 
          if (tex->surface.dcc_offset)
             meta = tex->surface.u.gfx9.dcc;
 
          if (tex->surface.dcc_offset)
             meta = tex->surface.u.gfx9.dcc;
-         else
-            meta = tex->surface.u.gfx9.htile;
 
          state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
                      S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
 
          state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
                      S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 5fef04b3cb2cf02237d5bda74bc190c680e92ebf..b20a59de1a1b9f7e62b6cdad0ddf6468ab515de0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2540,9 +2540,9 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su
 
          surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
          surf->db_htile_surface =
 
          surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
          surf->db_htile_surface =
-            S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
+            S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
          if (sctx->chip_class == GFX9) {
          if (sctx->chip_class == GFX9) {
-            surf->db_htile_surface |= S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
+            surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
          }
       }
    } else {
          }
       }
    } else {
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 2ec19e5f28d9462bbb24e4a2c588cba9160dcd1d..65a53e9f7ac9aa1877514417488285e1a92bce77 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1072,11 +1072,9 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
 
       if (tex->surface.htile_offset) {
          u_log_printf(log,
 
       if (tex->surface.htile_offset) {
          u_log_printf(log,
-                      "  HTile: offset=%" PRIu64 ", size=%u, alignment=%u, "
-                      "rb_aligned=%u, pipe_aligned=%u\n",
+                      "  HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n",
                       tex->surface.htile_offset, tex->surface.htile_size,
                       tex->surface.htile_offset, tex->surface.htile_size,
-                      tex->surface.htile_alignment, tex->surface.u.gfx9.htile.rb_aligned,
-                      tex->surface.u.gfx9.htile.pipe_aligned);
+                      tex->surface.htile_alignment);
       }
 
       if (tex->surface.dcc_offset) {
       }
 
       if (tex->surface.dcc_offset) {