radeonsi/nir: validate is_patch because SPIR-V doesn't set it for tess factors

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 803c3be4e7721cefffc5834a1fbfab7fa0f64a85..b1ab398ba71d8ae07b899801256e9e705a466b99 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1081,9 +1081,22 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
        LLVMValueRef dw_addr, stride;
+       ubyte name, index;
 
        driver_location = driver_location / 4;
 
+       if (load_input) {
+               name = info->input_semantic_name[driver_location];
+               index = info->input_semantic_index[driver_location];
+       } else {
+               name = info->output_semantic_name[driver_location];
+               index = info->output_semantic_index[driver_location];
+       }
+
+       assert((name == TGSI_SEMANTIC_PATCH ||
+               name == TGSI_SEMANTIC_TESSINNER ||
+               name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
+
        if (load_input) {
                stride = get_tcs_in_vertex_dw_stride(ctx);
                dw_addr = get_tcs_in_current_patch_offset(ctx);
@@ -1101,16 +1114,6 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
                param_index = LLVMConstInt(ctx->i32, const_index, 0);
        }
 
-       ubyte name;
-       ubyte index;
-       if (load_input) {
-               name = info->input_semantic_name[driver_location];
-               index = info->input_semantic_index[driver_location];
-       } else {
-               name = info->output_semantic_name[driver_location];
-               index = info->output_semantic_index[driver_location];
-       }
-
        dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
                                                      vertex_index, param_index,
                                                      name, index);
@@ -1186,6 +1189,10 @@ LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
        ubyte name = info->input_semantic_name[driver_location];
        ubyte index = info->input_semantic_index[driver_location];
 
+       assert((name == TGSI_SEMANTIC_PATCH ||
+               name == TGSI_SEMANTIC_TESSINNER ||
+               name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
+
        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
 
        if (!param_index) {
@@ -1350,6 +1357,10 @@ static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
        if (!param_index)
                param_index = LLVMConstInt(ctx->i32, const_index, 0);
 
+       assert((name == TGSI_SEMANTIC_PATCH ||
+               name == TGSI_SEMANTIC_TESSINNER ||
+               name == TGSI_SEMANTIC_TESSOUTER) == is_patch);
+
        if (!is_patch) {
                stride = get_tcs_out_vertex_dw_stride(ctx);
                dw_addr = get_tcs_out_current_patch_offset(ctx);