ac: add has_rbplus to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index b6b37564c9f7fb2076b892c5ee1d6cedf42cf841..50e92a405e336a38f2a626af646b3f1bb123ec08 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -454,6 +454,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                                        info->family == CHIP_RENOIR ||
                                        info->chip_class >= GFX10;
 
+       info->has_rbplus = info->family == CHIP_STONEY ||
+                          info->chip_class >= GFX9;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 10b578a1ef991db7c2baf7f4a02babf1011dd54b..173cc82084ab6a0ff63c0f8b5a5606dbb86556bc 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -61,6 +61,7 @@ struct radeon_info {
        bool                        has_clear_state;
        bool                        has_distributed_tess;
        bool                        has_dcc_constant_encode;
+       bool                        has_rbplus; /* if RB+ registers exist */
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a1927b9506c28d28c4a37692a7daad38d7f06d56..3726ad0ec787885b039632ecae210cbaa1d6fdb1 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -356,7 +356,6 @@ radv_physical_device_init(struct radv_physical_device *device,
 
        if (device->rad_info.family == CHIP_STONEY ||
            device->rad_info.chip_class >= GFX9) {
-               device->has_rbplus = true;
                device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
                                         device->rad_info.family == CHIP_VEGA12 ||
                                         device->rad_info.family == CHIP_RAVEN ||

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 584dddb48dfd05a00871f6f9f569800cfbe6eebd..97ab503bef31d49c1bb7d8982d915458cfc191bb 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
                blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
        }
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
                /* Disable RB+ blend optimizations for dual source blending. */
                if (blend.mrt0_is_dual_src) {
                        for (i = 0; i < 8; i++) {
@@ -3329,7 +3329,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
        radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
 
                radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
                radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
@@ -4054,7 +4054,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
        else
                z_order = V_02880C_LATE_Z;
 
-       bool disable_rbplus = device->physical_device->has_rbplus &&
+       bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
                              !device->physical_device->rbplus_allowed;
 
        /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 6c8d4b9c0a0048e205ecfefdc631ed552d1770bf..c507945e9eb3bda43bd35e022291028fb4c9f3dc 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -280,7 +280,6 @@ struct radv_physical_device {
        int master_fd;
        struct wsi_device                       wsi_device;
 
-       bool has_rbplus; /* if RB+ register exist */
        bool rbplus_allowed; /* if RB+ is allowed */
        bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 2d5298edd8cff8986c58cbf85476bdeb972f8e15..525202c7c2080d652e1473b0da6ca181a7e3858b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1181,8 +1181,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
         */
        if (sscreen->info.family == CHIP_STONEY ||
            sscreen->info.chip_class >= GFX9) {
-               sscreen->has_rbplus = true;
-
                sscreen->rbplus_allowed =
                        !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
                        (sscreen->info.family == CHIP_STONEY ||

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 7ad700f526539a521e0f0a324e813dea4569e4a6..f9371f97a96264f3c34c71f20dc175729ebf8074 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -512,7 +512,6 @@ struct si_screen {
        /* Whether shaders are monolithic (1-part) or separate (3-part). */
        bool                            use_monolithic_shaders;
        bool                            record_llvm_ir;
-       bool                            has_rbplus;     /* if RB+ registers exist */
        bool                            rbplus_allowed; /* if RB+ is allowed */
        bool                            dcc_msaa_allowed;
        bool                            cpdma_prefetch_writes_memory;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index cd26f5af9d2e98996b09134f0afdaa5a7cb8d3f5..dcd627467bc9edd9ac02a2038a8f8464368ed0ff 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1482,7 +1482,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
        if (!rs->multisample_enable)
                db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
 
-       if (sctx->screen->has_rbplus &&
+       if (sctx->screen->info.has_rbplus &&
            !sctx->screen->rbplus_allowed)
                db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);