radeonsi: don't invalidate VMEM L1 for memory barriers for index buffers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index ddf6cfe14dee0ec6f063b066b804caa906cae0e8..34f3ed7264b982584e3c94dc301a275ab4c5b444 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3366,6 +3366,7 @@ static void si_texture_barrier(struct pipe_context *ctx)
                         SI_CONTEXT_CS_PARTIAL_FLUSH;
 }
 
+/* This only ensures coherency for shader image/buffer stores. */
 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
 {
        struct si_context *sctx = (struct si_context *)ctx;
@@ -3392,9 +3393,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
        }
 
        if (flags & PIPE_BARRIER_INDEX_BUFFER) {
-               sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
-
-               /* Indices are read through TC L2 since VI. */
+               /* Indices are read through TC L2 since VI.
+                * L1 isn't used.
+                */
                if (sctx->screen->b.chip_class <= CIK)
                        sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
        }