freedreno/ir3: Use output type size to set OUTPUT_REG_HALF_PRECISION

Previously the A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION was set depending
on whether half_precision was set in the shader key. With support for
mediump precision, it is possible to have different outputs use
different precisions. That means we can’t have a global shader state
to specify it. Instead it now tries to copy the half-float-ness
from the nir_variable for the output into the ir3_shader_variant. This
is then used to decide whether to set half-precision for each output.

The a6xx version is copied from the a5xx code but it has not been
tested.

v2. [Hyunjun Ko (zzoon@igalia.com)] There's the half flag recently
added, which represents precision based on IR3_REG_HALF. Now use this
flag to avoid duplication.

Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 918c6585ac429fa93b2e068919989f76d3517098..e20bb2f6fc9fc96c5c206e83686a9d90bffbf989 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -606,8 +606,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
        OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
        for (i = 0; i < 8; i++) {
                OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
-                               COND(emit->key.half_precision,
-                                       A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
+                               COND(s[FS].v->outputs[i].half, A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
        }
 
 

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index b90ad2e06e5b6c0bb2a4500dcd977b0aa703fd81..b73d2031ab3d1c9af3ef826977012519c74d55f0 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -626,11 +626,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
 
        OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
        for (i = 0; i < 8; i++) {
-               // TODO we could have a mix of half and full precision outputs,
-               // we really need to figure out half-precision from IR3_REG_HALF
                OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
-                               COND(false,
-                                       A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
+                               COND(s[FS].v->outputs[i].half, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
        }
 
        OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);