winsys/amdgpu,radeon: pass vm_alignment to buffer_from_handle
authorMarek Olšák <marek.olsak@amd.com>
Mon, 26 Nov 2018 22:06:20 +0000 (17:06 -0500)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 29 Nov 2018 01:20:27 +0000 (20:20 -0500)
Acked-by: Christian König <christian.koenig@amd.com>
src/gallium/drivers/r300/r300_texture.c
src/gallium/drivers/r600/r600_texture.c
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/drivers/radeonsi/si_texture.c
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index 6f8893eee6c995567050b05bef5a68796e463798..46d88b34638c3b22851d61fe5c73c17a38b0f757 100644 (file)
@@ -1182,7 +1182,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
         return NULL;
     }
 
-    buffer = rws->buffer_from_handle(rws, whandle, &stride, NULL);
+    buffer = rws->buffer_from_handle(rws, whandle, 0, &stride, NULL);
     if (!buffer)
         return NULL;
 
index def4cbf86b23f0e5f2e0fab7b8f07eb111d8d199..71606df38d93a4656ba2377e08b1a007c65b7c0e 100644 (file)
@@ -1108,7 +1108,9 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
              templ->depth0 != 1 || templ->last_level != 0)
                return NULL;
 
-       buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
+       buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+                                             rscreen->info.max_alignment,
+                                             &stride, &offset);
        if (!buf)
                return NULL;
 
@@ -1852,6 +1854,7 @@ r600_memobj_from_handle(struct pipe_screen *screen,
                return NULL;
 
        buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+                                             rscreen->info.max_alignment,
                                              &stride, &offset);
        if (!buf) {
                free(memobj);
index a56ff75ad242f594244574c9db2dc387e6b1d5e2..6c03999d212129e8cf5bd65e14180e8dbaab18a6 100644 (file)
@@ -364,6 +364,7 @@ struct radeon_winsys {
      */
     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
                                             struct winsys_handle *whandle,
+                                            unsigned vm_alignment,
                                             unsigned *stride, unsigned *offset);
 
     /**
index 2fb79253a72dc746bca4de90d1973517de81d02a..95f1e8c9693b6c4d8fdacc4df87fb3856943b341 100644 (file)
@@ -1487,7 +1487,9 @@ static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
              templ->depth0 != 1 || templ->last_level != 0)
                return NULL;
 
-       buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset);
+       buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+                                             sscreen->info.max_alignment,
+                                             &stride, &offset);
        if (!buf)
                return NULL;
 
@@ -2338,6 +2340,7 @@ si_memobj_from_handle(struct pipe_screen *screen,
                return NULL;
 
        buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+                                             sscreen->info.max_alignment,
                                              &stride, &offset);
        if (!buf) {
                free(memobj);
index 36041133d0dd78785e3480bec31eca313d5a7afc..e32e23361f4a5578dff02b5612311117e40ea299 100644 (file)
@@ -1397,6 +1397,7 @@ no_slab:
 
 static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
                                                struct winsys_handle *whandle,
+                                               unsigned vm_alignment,
                                                unsigned *stride,
                                                unsigned *offset)
 {
@@ -1454,7 +1455,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
       goto error;
 
    r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
-                             result.alloc_size, 1 << 20, 0, &va, &va_handle,
+                             result.alloc_size, vm_alignment, 0, &va, &va_handle,
                             AMDGPU_VA_RANGE_HIGH);
    if (r)
       goto error;
index 07a9b2d758e550a78f46cd305d73a1b5a2f69a98..d1e2a8685ba91a5932bc21652b980668e68fd9e2 100644 (file)
@@ -1134,6 +1134,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
 
 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
                                                       struct winsys_handle *whandle,
+                                                      unsigned vm_alignment,
                                                       unsigned *stride,
                                                       unsigned *offset)
 {
@@ -1239,7 +1240,7 @@ done:
     if (ws->info.r600_has_virtual_memory && !bo->va) {
         struct drm_radeon_gem_va va;
 
-        bo->va = radeon_bomgr_find_va64(ws, bo->base.size, 1 << 20);
+        bo->va = radeon_bomgr_find_va64(ws, bo->base.size, vm_alignment);
 
         va.handle = bo->handle;
         va.operation = RADEON_VA_MAP;
index cf07a8d8e266ca319290a73dbc5535e73354b0f3..293372cc26d09111584e414f3dfbb7366f0450a4 100644 (file)
@@ -589,6 +589,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     /* 2D tiling on CIK is supported since DRM 2.35.0 */
     ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
+    ws->info.max_alignment = 1024*1024;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;