gallium/radeon: simplify disabling render condition for u_blitter
authorMarek Olšák <marek.olsak@amd.com>
Sat, 7 Nov 2015 13:45:58 +0000 (14:45 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Fri, 13 Nov 2015 18:54:41 +0000 (19:54 +0100)
just disable it by not setting the predication bit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/r600/r600_blit.c
src/gallium/drivers/r600/r600_state_common.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeonsi/si_blit.c
src/gallium/drivers/radeonsi/si_state_draw.c

index fff841c0ded0f7706773ce61d6e98ffa384ed804..8a90489318ed9f70d517f73ab82b1c032e84591d 100644 (file)
@@ -87,18 +87,16 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
                        (struct pipe_sampler_view**)rctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
        }
 
-       if ((op & R600_DISABLE_RENDER_COND) && rctx->b.current_render_cond) {
-           util_blitter_save_render_condition(rctx->blitter,
-                                              rctx->b.current_render_cond,
-                                              rctx->b.current_render_cond_cond,
-                                              rctx->b.current_render_cond_mode);
-        }
+       if (op & R600_DISABLE_RENDER_COND)
+               rctx->b.render_cond_force_off = true;
 }
 
 static void r600_blitter_end(struct pipe_context *ctx)
 {
        struct r600_context *rctx = (struct r600_context *)ctx;
-        r600_resume_nontimer_queries(&rctx->b);
+
+       rctx->b.render_cond_force_off = false;
+       r600_resume_nontimer_queries(&rctx->b);
 }
 
 static unsigned u_max_sample(struct pipe_resource *r)
index eb5436197c6c034fe88361995af74aee8955496e..28aedffc42d16f838aa9896985013b26b9318b78 100644 (file)
@@ -1478,6 +1478,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
        struct pipe_draw_info info = *dinfo;
        struct pipe_index_buffer ib = {};
        struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+       bool render_cond_bit = rctx->b.predicate_drawing && !rctx->b.render_cond_force_off;
        uint64_t mask;
 
        if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
@@ -1696,7 +1697,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                if (ib.user_buffer) {
                        unsigned size_bytes = info.count*ib.index_size;
                        unsigned size_dw = align(size_bytes, 4) / 4;
-                       cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
+                       cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit);
                        cs->buf[cs->cdw++] = info.count;
                        cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
                        memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
@@ -1705,7 +1706,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                        uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
 
                        if (likely(!info.indirect)) {
-                               cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
+                               cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit);
                                cs->buf[cs->cdw++] = va;
                                cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
                                cs->buf[cs->cdw++] = info.count;
@@ -1732,7 +1733,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                                cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0);
                                cs->buf[cs->cdw++] = max_size;
 
-                               cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, rctx->b.predicate_drawing);
+                               cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit);
                                cs->buf[cs->cdw++] = info.indirect_offset;
                                cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
                        }
@@ -1758,11 +1759,11 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                }
 
                if (likely(!info.indirect)) {
-                       cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
+                       cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit);
                        cs->buf[cs->cdw++] = info.count;
                }
                else {
-                       cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, rctx->b.predicate_drawing);
+                       cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit);
                        cs->buf[cs->cdw++] = info.indirect_offset;
                }
                cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
index 2e3f1547e45ab663f32191af6a4605a87f1491e5..139c377cd6e58862becc95cff83b4209fa8e4ce5 100644 (file)
@@ -420,7 +420,8 @@ struct r600_common_context {
        struct pipe_query               *current_render_cond;
        unsigned                        current_render_cond_mode;
        boolean                         current_render_cond_cond;
-       boolean                         predicate_drawing;
+       bool                            predicate_drawing;
+       bool                            render_cond_force_off; /* for u_blitter */
        /* For context flushing. */
        struct pipe_query               *saved_render_cond;
        boolean                         saved_render_cond_cond;
index 31f22c4acf71c92ab75029e27557d9c900b58e9b..13d8e6f2a5f26833d60e6f107b07f125202fac33 100644 (file)
@@ -86,17 +86,15 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
                        sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
        }
 
-       if ((op & SI_DISABLE_RENDER_COND) && sctx->b.current_render_cond) {
-               util_blitter_save_render_condition(sctx->blitter,
-                                                   sctx->b.current_render_cond,
-                                                   sctx->b.current_render_cond_cond,
-                                                   sctx->b.current_render_cond_mode);
-       }
+       if (op & SI_DISABLE_RENDER_COND)
+               sctx->b.render_cond_force_off = true;
 }
 
 static void si_blitter_end(struct pipe_context *ctx)
 {
        struct si_context *sctx = (struct si_context *)ctx;
+
+       sctx->b.render_cond_force_off = false;
        r600_resume_nontimer_queries(&sctx->b);
 }
 
index 3015374c648c429a2a029177784ac71d325ac401..ebc01e8e4aeb424c4e284f785d4322d6c741d77a 100644 (file)
@@ -457,6 +457,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
 {
        struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
        unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
+       bool render_cond_bit = sctx->b.predicate_drawing && !sctx->b.render_cond_force_off;
 
        if (info->count_from_stream_output) {
                struct r600_so_target *t =
@@ -563,7 +564,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
                        radeon_emit(cs, index_max_size);
 
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing));
+                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
                        radeon_emit(cs, info->indirect_offset);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
@@ -571,7 +572,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
                } else {
                        index_va += info->start * ib->index_size;
 
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing));
+                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
                        radeon_emit(cs, index_max_size);
                        radeon_emit(cs, index_va);
                        radeon_emit(cs, (index_va >> 32UL) & 0xFF);
@@ -590,13 +591,13 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, indirect_va);
                        radeon_emit(cs, indirect_va >> 32);
 
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing));
+                       radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
                        radeon_emit(cs, info->indirect_offset);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
                        radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
                        radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
                } else {
-                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing));
+                       radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
                        radeon_emit(cs, info->count);
                        radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
                                    S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));