r600: align for mipmap tree changes

diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 20965bb3c844c9599edccb1f0413e4e7e9d39513..9d83a64e22018941a83693feb10f17f89d15407d 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -312,16 +312,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target,
        case GL_TEXTURE_MAX_LEVEL:
        case GL_TEXTURE_MIN_LOD:
        case GL_TEXTURE_MAX_LOD:
-               /* This isn't the most efficient solution but there doesn't appear to
-                * be a nice alternative.  Since there's no LOD clamping,
-                * we just have to rely on loading the right subset of mipmap levels
-                * to simulate a clamped LOD.
-                */
-               if (t->mt) {
-                       radeon_miptree_unreference(t->mt);
-                       t->mt = 0;
-                       t->validated = GL_FALSE;
-               }
+               t->validated = GL_FALSE;
                break;
 
        case GL_DEPTH_TEXTURE_MODE:
@@ -369,10 +360,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
                t->bo = NULL;
        }
 
-       if (t->mt) {
-               radeon_miptree_unreference(t->mt);
-               t->mt = 0;
-       }
+       radeon_miptree_unreference(&t->mt);
+
        _mesa_delete_texture_object(ctx, texObj);
 }
 

diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 27c8354923cc4ed1c1f8f0accbb98820cdab1873..4ec315b78c7439a8f053bf96db3a3aeae4d1d19c 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -649,7 +649,6 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 {
        radeonTexObj *t = radeon_tex_obj(texObj);
        const struct gl_texture_image *firstImage;
-       int firstlevel = t->mt ? t->mt->firstLevel : 0;
        GLuint uTexelPitch, row_align;
 
        if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
@@ -657,7 +656,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
            t->bo)
                return;
 
-       firstImage = t->base.Image[0][firstlevel];
+       firstImage = t->base.Image[0][t->minLod];
 
        if (!t->image_override) {
                if (!r600GetTexFormat(texObj, firstImage->TexFormat)) {
@@ -692,7 +691,8 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
        }
 
        row_align = rmesa->radeon.texture_row_align - 1;
-       uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp;
+       uTexelPitch = (_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align;
+       uTexelPitch = uTexelPitch / _mesa_get_format_bytes(firstImage->TexFormat);
        uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
                & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
@@ -706,10 +706,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
        SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
                 TEX_HEIGHT_shift, TEX_HEIGHT_mask);
 
-       if ((t->mt->lastLevel - t->mt->firstLevel) > 0) {
-               t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256;
-               SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask);
-               SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask);
+       if ((t->maxLod - t->minLod) > 0) {
+               t->SQ_TEX_RESOURCE3 = t->mt->levels[t->minLod].size / 256;
+               SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
+               SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
        }
 }
 
@@ -808,9 +808,8 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
        struct gl_texture_object *tObj =
            _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
        radeonTexObjPtr t = radeon_tex_obj(tObj);
-       int firstlevel = t->mt ? t->mt->firstLevel : 0;
        const struct gl_texture_image *firstImage;
-       uint32_t pitch_val, size, row_align, bpp;
+       uint32_t pitch_val, size, row_align;
 
        if (!tObj)
                return;
@@ -820,13 +819,9 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
        if (!offset)
                return;
 
-       bpp = depth / 8;
-       if (bpp == 3) 
-               bpp = 4;
-
-       firstImage = t->base.Image[0][firstlevel];
+       firstImage = t->base.Image[0][t->minLod];
        row_align = rmesa->radeon.texture_row_align - 1;
-       size = ((firstImage->Width * bpp + row_align) & ~row_align) * firstImage->Height;
+       size = ((_mesa_format_row_stride(firstImage->TexFormat, firstImage->Width) + row_align) & ~row_align) * firstImage->Height;
        if (t->bo) {
                radeon_bo_unref(t->bo);
                t->bo = NULL;
@@ -949,14 +944,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
                radeon_bo_unref(rImage->bo);
                rImage->bo = NULL;
        }
-       if (t->mt) {
-               radeon_miptree_unreference(t->mt);
-               t->mt = NULL;
-       }
-       if (rImage->mt) {
-               radeon_miptree_unreference(rImage->mt);
-               rImage->mt = NULL;
-       }
+
+       radeon_miptree_unreference(&t->mt);
+       radeon_miptree_unreference(&rImage->mt);
+
        _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
                                   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
        texImage->RowStride = rb->pitch / rb->cpp;

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index ec76fbcb6daa4a173e34b3df7541f210cbebb0e9..2b2b4d748f6c7e74ebf4d49f1316f89ca0f64b22 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -54,11 +54,15 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
                if (ctx->Texture.Unit[i]._ReallyEnabled) {
                        radeonTexObj *t = r700->textures[i];
+                       uint32_t offset;
                        if (t) {
-                               if (!t->image_override)
+                               if (!t->image_override) {
                                        bo = t->mt->bo;
-                               else
+                                       offset = get_base_teximage_offset(t);
+                               } else {
                                        bo = t->bo;
+                                       offset = 0;
+                               }
                                if (bo) {
 
                                        r700SyncSurf(context, bo,
@@ -77,7 +81,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
                                        R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
                                                             bo,
-                                                            0,
+                                                            offset,
                                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
                                        R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
                                                             bo,