radv: Optimize emitting index buffer changes.

Since the direct indexed draw packet has the address/count info
inline, there is no sense in emitting the base and size.

No real significant changes found during benchmarks.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3466>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 549b7e8843d8b1cdebdbc99e456af3dc45442973..12d5d60d91aba5f0817422f4f8032eabbb8a4083 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2063,7 +2063,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 }
 
 static void
-radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
+radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
 {
        struct radeon_cmdbuf *cs = cmd_buffer->cs;
        struct radv_cmd_state *state = &cmd_buffer->state;
@@ -2081,6 +2081,11 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
                state->last_index_type = state->index_type;
        }
 
+       /* For the direct indexed draws we use DRAW_INDEX_2, which includes
+        * the index_va and max_index_count already. */
+       if (!indirect)
+               return;
+
        radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
        radeon_emit(cs, state->index_va);
        radeon_emit(cs, state->index_va >> 32);
@@ -4665,7 +4670,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
 
        if (info->indexed) {
                if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
-                       radv_emit_index_buffer(cmd_buffer);
+                       radv_emit_index_buffer(cmd_buffer, info->indirect);
        } else {
                /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
                 * so the state must be re-emitted before the next indexed