radv: Consolidate GFX9 merged shader lookup logic

This was being handled in a few different places, consolidate it into a
single radv_get_shader() function.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "18.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 04ce30c87688edfcb769dcd778471bf2a30ac5fb..e9b1dffc1cdb4589de3b209c3810cc47daa41a4a 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -560,20 +560,8 @@ radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
                      gl_shader_stage stage,
                      int idx)
 {
-       if (stage == MESA_SHADER_VERTEX) {
-               if (pipeline->shaders[MESA_SHADER_VERTEX])
-                       return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
-               if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
-                       return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
-               if (pipeline->shaders[MESA_SHADER_GEOMETRY])
-                       return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
-       } else if (stage == MESA_SHADER_TESS_EVAL) {
-               if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
-                       return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
-               if (pipeline->shaders[MESA_SHADER_GEOMETRY])
-                       return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
-       }
-       return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
+       struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
+       return &shader->info.user_sgprs_locs.shader_data[idx];
 }
 
 static void
@@ -1639,7 +1627,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
        if ((pipeline_is_dirty ||
            (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
            cmd_buffer->state.pipeline->vertex_elements.count &&
-           radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
+           radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
                struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
                unsigned vb_offset;
                void *vb_ptr;
@@ -2940,7 +2928,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
        struct radeon_winsys_cs *cs = cmd_buffer->cs;
        unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
                                      : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
-       bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
+       bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
        uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
        assert(base_reg);
 

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7a44544f44e5be07e0519c838eb447cc862f0fff..ff647ed9af300b90074a57f3dfa893fe510503d4 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1583,21 +1583,23 @@ static void si_multiwave_lds_size_workaround(struct radv_device *device,
 }
 
 struct radv_shader_variant *
-radv_get_vertex_shader(struct radv_pipeline *pipeline)
+radv_get_shader(struct radv_pipeline *pipeline,
+               gl_shader_stage stage)
 {
-       if (pipeline->shaders[MESA_SHADER_VERTEX])
-               return pipeline->shaders[MESA_SHADER_VERTEX];
-       if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
-               return pipeline->shaders[MESA_SHADER_TESS_CTRL];
-       return pipeline->shaders[MESA_SHADER_GEOMETRY];
-}
-
-static struct radv_shader_variant *
-radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
-{
-       if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
-               return pipeline->shaders[MESA_SHADER_TESS_EVAL];
-       return pipeline->shaders[MESA_SHADER_GEOMETRY];
+       if (stage == MESA_SHADER_VERTEX) {
+               if (pipeline->shaders[MESA_SHADER_VERTEX])
+                       return pipeline->shaders[MESA_SHADER_VERTEX];
+               if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
+                       return pipeline->shaders[MESA_SHADER_TESS_CTRL];
+               if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+                       return pipeline->shaders[MESA_SHADER_GEOMETRY];
+       } else if (stage == MESA_SHADER_TESS_EVAL) {
+               if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
+                       return pipeline->shaders[MESA_SHADER_TESS_EVAL];
+               if (pipeline->shaders[MESA_SHADER_GEOMETRY])
+                       return pipeline->shaders[MESA_SHADER_GEOMETRY];
+       }
+       return pipeline->shaders[stage];
 }
 
 static struct radv_tessellation_state
@@ -1632,7 +1634,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
                S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
        tess.num_patches = num_patches;
 
-       struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
+       struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
        unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
 
        switch (tes->info.tes.primitive_mode) {
@@ -3146,7 +3148,7 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
 
        unsigned vtx_reuse_depth = 30;
        if (radv_pipeline_has_tess(pipeline) &&
-           radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+           radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
                vtx_reuse_depth = 14;
        }
        radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
@@ -3307,7 +3309,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
        if (radv_pipeline_has_tess(pipeline)) {
                /* SWITCH_ON_EOI must be set if PrimID is used. */
                if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
-                   radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
+                   radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
                        ia_multi_vgt_param.ia_switch_on_eoi = true;
        }
 
@@ -3497,7 +3499,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
        if (loc->sgpr_idx != -1) {
                pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
                pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
-               if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
+               if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
                        pipeline->graphics.vtx_emit_num = 3;
                else
                        pipeline->graphics.vtx_emit_num = 2;

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 518f11dbcbf3b40160ab8f7a9820337cb4de4576..316fbc9af1d218225a2901ece067a672c378e3df 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1316,7 +1316,8 @@ struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
                                                 gl_shader_stage stage,
                                                 int idx);
 
-struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
+struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
+                                           gl_shader_stage stage);
 
 struct radv_graphics_pipeline_create_info {
        bool use_rectlist;