r600g: fix up shader out misc stuff for copy shader
authorDave Airlie <airlied@redhat.com>
Wed, 29 Jan 2014 00:17:15 +0000 (00:17 +0000)
committerDave Airlie <airlied@redhat.com>
Wed, 5 Feb 2014 00:49:42 +0000 (10:49 +1000)
set the correct values so the misc out register is setup correctly
for the copy shader.

This also updates the state for the gs copy shader so the hw
gets programmed correctly.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_state_common.c

index 0a9f55a94a08b7995aa4b872da85da4b88ff4f16..3535a134715b28ef4294cf669cf1b469cfdef58d 100644 (file)
@@ -1162,7 +1162,7 @@ static int generate_gs_copy_shader(struct r600_context *rctx,
        struct r600_bytecode_output output;
        struct r600_bytecode_cf *cf_jump, *cf_pop,
                *last_exp_pos = NULL, *last_exp_param = NULL;
-       int i, next_clip_pos = 62, next_param = 0;
+       int i, next_clip_pos = 61, next_param = 0;
 
        cshader = calloc(1, sizeof(struct r600_pipe_shader));
        if (!cshader)
@@ -1263,18 +1263,26 @@ static int generate_gs_copy_shader(struct r600_context *rctx,
 
                case TGSI_SEMANTIC_PSIZE:
                        output.array_base = 61;
+                       if (next_clip_pos == 61)
+                               next_clip_pos = 62;
                        output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
                        output.swizzle_y = 7;
                        output.swizzle_z = 7;
                        output.swizzle_w = 7;
+                       ctx.shader->vs_out_misc_write = 1;
+                       ctx.shader->vs_out_point_size = 1;
                        break;
                case TGSI_SEMANTIC_LAYER:
                        output.array_base = 61;
+                       if (next_clip_pos == 61)
+                               next_clip_pos = 62;
                        output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
                        output.swizzle_x = 7;
                        output.swizzle_y = 7;
                        output.swizzle_z = 0;
                        output.swizzle_w = 7;
+                       ctx.shader->vs_out_misc_write = 1;
+                       ctx.shader->vs_out_layer = 1;
                        break;
                case TGSI_SEMANTIC_CLIPDIST:
                        /* spi_sid is 0 for clipdistance outputs that were generated
index f237d26c3763b304708c1c61c130d664656c5beb..ffa1eb0c4907bd501fce69373584125f17a396d3 100644 (file)
@@ -1171,6 +1171,13 @@ static bool r600_update_derived_state(struct r600_context *rctx)
                if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
                        update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
                        update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
+                       /* Update clip misc state. */
+                       if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+                                       rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+                               rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
+                               rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
+                               rctx->clip_misc_state.atom.dirty = true;
+                       }
                }
 
                r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);