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62e36ba)
it only counts stores
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
/* For a crazy dEQP test containing 2597 memory opcodes, mostly
* buffer stores. */
/* For a crazy dEQP test containing 2597 memory opcodes, mostly
* buffer stores. */
- return sel->info.stage == MESA_SHADER_COMPUTE && sel->info.num_memory_instructions > 1000;
+ return sel->info.stage == MESA_SHADER_COMPUTE && sel->info.num_memory_stores > 1000;
}
static struct nir_shader *get_nir_shader(struct si_shader_selector *sel, bool *free_nir)
}
static struct nir_shader *get_nir_shader(struct si_shader_selector *sel, bool *free_nir)
int constbuf0_num_slots;
ubyte num_stream_output_components[4];
int constbuf0_num_slots;
ubyte num_stream_output_components[4];
- uint num_memory_instructions; /**< sampler, buffer, and image instructions */
+ uint num_memory_stores;
ubyte colors_read; /**< which color components are read by the FS */
ubyte colors_written;
ubyte colors_read; /**< which color components are read by the FS */
ubyte colors_written;
case nir_intrinsic_bindless_image_store:
info->uses_bindless_images = true;
info->writes_memory = true;
case nir_intrinsic_bindless_image_store:
info->uses_bindless_images = true;
info->writes_memory = true;
- info->num_memory_instructions++; /* we only care about stores */
+ info->num_memory_stores++;
break;
case nir_intrinsic_image_deref_store:
info->writes_memory = true;
break;
case nir_intrinsic_image_deref_store:
info->writes_memory = true;
- info->num_memory_instructions++; /* we only care about stores */
+ info->num_memory_stores++;
break;
case nir_intrinsic_bindless_image_atomic_add:
case nir_intrinsic_bindless_image_atomic_imin:
break;
case nir_intrinsic_bindless_image_atomic_add:
case nir_intrinsic_bindless_image_atomic_imin:
case nir_intrinsic_bindless_image_atomic_comp_swap:
info->uses_bindless_images = true;
info->writes_memory = true;
case nir_intrinsic_bindless_image_atomic_comp_swap:
info->uses_bindless_images = true;
info->writes_memory = true;
- info->num_memory_instructions++; /* we only care about stores */
+ info->num_memory_stores++;
break;
case nir_intrinsic_image_deref_atomic_add:
case nir_intrinsic_image_deref_atomic_imin:
break;
case nir_intrinsic_image_deref_atomic_add:
case nir_intrinsic_image_deref_atomic_imin:
case nir_intrinsic_image_deref_atomic_inc_wrap:
case nir_intrinsic_image_deref_atomic_dec_wrap:
info->writes_memory = true;
case nir_intrinsic_image_deref_atomic_inc_wrap:
case nir_intrinsic_image_deref_atomic_dec_wrap:
info->writes_memory = true;
- info->num_memory_instructions++; /* we only care about stores */
+ info->num_memory_stores++;
break;
case nir_intrinsic_store_ssbo:
case nir_intrinsic_ssbo_atomic_add:
break;
case nir_intrinsic_store_ssbo:
case nir_intrinsic_ssbo_atomic_add:
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_ssbo_atomic_comp_swap:
info->writes_memory = true;
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_ssbo_atomic_comp_swap:
info->writes_memory = true;
- info->num_memory_instructions++; /* we only care about stores */
+ info->num_memory_stores++;
break;
case nir_intrinsic_load_color0:
case nir_intrinsic_load_color1: {
break;
case nir_intrinsic_load_color0:
case nir_intrinsic_load_color1: {