radv: Select correct entries for binning.

Overshot it by one every time.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4c794d9515d5732af84284a8eef9cc974fd02094..27e13a2251c16f8175612023cea0e00acfd8992b 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2468,7 +2468,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
        }
 
        const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
-       while(color_entry->bpp <= color_bytes_per_pixel)
+       while(color_entry[1].bpp <= color_bytes_per_pixel)
                ++color_entry;
 
        extent = color_entry->extent;
@@ -2482,7 +2482,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
                unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
 
                const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
-               while(ds_entry->bpp <= ds_bytes_per_pixel)
+               while(ds_entry[1].bpp <= ds_bytes_per_pixel)
                        ++ds_entry;
 
                extent.width = MIN2(extent.width, ds_entry->extent.width);