radv/gfx9: use a bigger hammer to flush cb/db caches.

amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.

Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.

Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (for now :-)
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 972d37948aae89da5d73d0ae047155e17ba76dd6..a6981c136e70c5ce4ed2b832cb52804378f0f659 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -991,6 +991,11 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
        if (chip_class >= GFX9 && flush_cb_db) {
                unsigned cb_db_event, tc_flags;
 
+#if 0
+               /* This breaks a bunch of:
+                  dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
+                  use the big hammer always.
+               */
                /* Set the CB/DB flush event. */
                switch (flush_cb_db) {
                case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
@@ -1003,7 +1008,9 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
                        /* both CB & DB */
                        cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
                }
-
+#else
+               cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
+#endif
                /* TC    | TC_WB         = invalidate L2 data
                 * TC_MD | TC_WB         = invalidate L2 metadata
                 * TC    | TC_WB | TC_MD = invalidate L2 data & metadata