radeonsi: stop using TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION / VS_BLIT_SGPRS_AMD

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>

diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
index cc3ff50e8e06e2f6f51f9334a26cf7fdd3cd0c83..e8e04933fcab6a0dfbaec1f8a9a6322b20f1c437 100644 (file)
--- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
+++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
@@ -90,7 +90,7 @@ static LLVMValueRef ngg_get_vertices_per_prim(struct si_shader_context *ctx, uns
    const struct si_shader_info *info = &ctx->shader->selector->info;
 
    if (ctx->stage == MESA_SHADER_VERTEX) {
    const struct si_shader_info *info = &ctx->shader->selector->info;
 
    if (ctx->stage == MESA_SHADER_VERTEX) {

-      if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
+      if (info->base.vs.blit_sgprs_amd) {

          /* Blits always use axis-aligned rectangles with 3 vertices. */
          *num_vertices = 3;
          return LLVMConstInt(ctx->ac.i32, 3, 0);
          /* Blits always use axis-aligned rectangles with 3 vertices. */
          *num_vertices = 3;
          return LLVMConstInt(ctx->ac.i32, 3, 0);


@@ -1322,7 +1322,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi, unsigned max_outputs, LL
    }
 
    /* Update query buffer */
    }
 
    /* Update query buffer */

-   if (ctx->screen->use_ngg_streamout && !info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
+   if (ctx->screen->use_ngg_streamout && !info->base.vs.blit_sgprs_amd) {

       assert(!unterminated_es_if_block);
 
       tmp = si_unpack_param(ctx, ctx->vs_state_bits, 6, 1);
       assert(!unterminated_es_if_block);
 
       tmp = si_unpack_param(ctx, ctx->vs_state_bits, 6, 1);

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 823ec198714713202b8a0dbf13f4c20230cc034a..c77585256573db6448ae06571e333963006eeb2b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -387,7 +387,6 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
    unsigned num_returns = 0;
    unsigned num_prolog_vgprs = 0;
    unsigned stage = ctx->stage;
    unsigned num_returns = 0;
    unsigned num_prolog_vgprs = 0;
    unsigned stage = ctx->stage;

-   unsigned vs_blit_property = shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];

 
    memset(&ctx->args, 0, sizeof(ctx->args));
 
 
    memset(&ctx->args, 0, sizeof(ctx->args));
 


@@ -403,8 +402,8 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
    case MESA_SHADER_VERTEX:
       declare_global_desc_pointers(ctx);
 
    case MESA_SHADER_VERTEX:
       declare_global_desc_pointers(ctx);
 

-      if (vs_blit_property) {
-         declare_vs_blit_inputs(ctx, vs_blit_property);
+      if (shader->selector->info.base.vs.blit_sgprs_amd) {
+         declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd);

 
          /* VGPRs */
          declare_vs_input_vgprs(ctx, &num_prolog_vgprs, ngg_cull_shader);
 
          /* VGPRs */
          declare_vs_input_vgprs(ctx, &num_prolog_vgprs, ngg_cull_shader);


@@ -523,14 +522,14 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
                  NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
 
       declare_global_desc_pointers(ctx);
                  NULL); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
 
       declare_global_desc_pointers(ctx);

-      if (ctx->stage != MESA_SHADER_VERTEX || !vs_blit_property) {
+      if (ctx->stage != MESA_SHADER_VERTEX || !shader->selector->info.base.vs.blit_sgprs_amd) {

          declare_per_stage_desc_pointers(
             ctx, (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL));
       }
 
       if (ctx->stage == MESA_SHADER_VERTEX) {
          declare_per_stage_desc_pointers(
             ctx, (ctx->stage == MESA_SHADER_VERTEX || ctx->stage == MESA_SHADER_TESS_EVAL));
       }
 
       if (ctx->stage == MESA_SHADER_VERTEX) {

-         if (vs_blit_property)
-            declare_vs_blit_inputs(ctx, vs_blit_property);
+         if (shader->selector->info.base.vs.blit_sgprs_amd)
+            declare_vs_blit_inputs(ctx, shader->selector->info.base.vs.blit_sgprs_amd);

          else
             declare_vs_specific_input_sgprs(ctx);
       } else {
          else
             declare_vs_specific_input_sgprs(ctx);
       } else {

diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
index 83bea6cf4995ab803f8003d32b254a2f83536275..daa992b42d01c36f199eedf2aa7c2fba814330ee 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
@@ -41,7 +41,7 @@ static LLVMValueRef unpack_sint16(struct si_shader_context *ctx, LLVMValueRef i3
 static void load_input_vs(struct si_shader_context *ctx, unsigned input_index, LLVMValueRef out[4])
 {
    const struct si_shader_info *info = &ctx->shader->selector->info;
 static void load_input_vs(struct si_shader_context *ctx, unsigned input_index, LLVMValueRef out[4])
 {
    const struct si_shader_info *info = &ctx->shader->selector->info;

-   unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+   unsigned vs_blit_property = info->base.vs.blit_sgprs_amd;

 
    if (vs_blit_property) {
       LLVMValueRef vertex_id = ctx->abi.vertex_id;
 
    if (vs_blit_property) {
       LLVMValueRef vertex_id = ctx->abi.vertex_id;

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index a3dc554e5a9a3adf8803c16d91240172dd040bb5..c26ddd30db0015592c8e389f36a24e0489253d56 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -456,11 +456,6 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
    info->base = nir->info;
    info->stage = nir->info.stage;
 
    info->base = nir->info;
    info->stage = nir->info.stage;
 

-   if (nir->info.stage == MESA_SHADER_VERTEX) {
-      info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] = nir->info.vs.window_space_position;
-      info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] = nir->info.vs.blit_sgprs_amd;
-   }
-

    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
       info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] = nir->info.tess.tcs_vertices_out;
    }
    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
       info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] = nir->info.tess.tcs_vertices_out;
    }

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e8df29ba6134ea2cee9b032e2db349e182a15af7..0aa644466b3526292ba275626a593d08d99b5ce7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -732,7 +732,8 @@ static void si_emit_clip_regs(struct si_context *sctx)
    struct si_shader_selector *vs_sel = vs->selector;
    struct si_shader_info *info = &vs_sel->info;
    struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
    struct si_shader_selector *vs_sel = vs->selector;
    struct si_shader_info *info = &vs_sel->info;
    struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;

-   unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+   bool window_space = info->stage == MESA_SHADER_VERTEX ?
+                          info->base.vs.window_space_position : 0;

    unsigned clipdist_mask = vs_sel->clipdist_mask;
    unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
    unsigned culldist_mask = vs_sel->culldist_mask;
    unsigned clipdist_mask = vs_sel->clipdist_mask;
    unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
    unsigned culldist_mask = vs_sel->culldist_mask;

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index c7a3f992a212172490bd02fd32ec0be80c4848d7..9fccc4dd3e52ceed7c9d76fc51d965276837e730 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1827,7 +1827,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
        (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
        (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
        (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
        (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
        (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
        (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&

-       !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
+       !sctx->vs_shader.cso->info.base.vs.window_space_position &&

        !sctx->vs_shader.cso->so.num_outputs &&
 #else
        (sctx->vs_shader.cso->prim_discard_cs_allowed ||
        !sctx->vs_shader.cso->so.num_outputs &&
 #else
        (sctx->vs_shader.cso->prim_discard_cs_allowed ||

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 902b146be988c173d0afa2682de801cd4561ed25..c629c28fa614c12304968640e81c3b48089d6a2e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1064,7 +1064,8 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
    unsigned num_user_sgprs;
    unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
    uint64_t va;
    unsigned num_user_sgprs;
    unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
    uint64_t va;

-   unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+   bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
+                          gs_info->base.vs.window_space_position : 0;

    bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
    unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
    unsigned input_prim = si_get_input_prim(gs_sel);
    bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
    unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
    unsigned input_prim = si_get_input_prim(gs_sel);


@@ -1086,9 +1087,9 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
    if (es_stage == MESA_SHADER_VERTEX) {
       es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
 
    if (es_stage == MESA_SHADER_VERTEX) {
       es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
 

-      if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
+      if (es_info->base.vs.blit_sgprs_amd) {

          num_user_sgprs =
          num_user_sgprs =

-            SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+            SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;

       } else {
          num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
       }
       } else {
          num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
       }


@@ -1346,7 +1347,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
    unsigned num_user_sgprs, vgpr_comp_cnt;
    uint64_t va;
    unsigned nparams, oc_lds_en;
    unsigned num_user_sgprs, vgpr_comp_cnt;
    uint64_t va;
    unsigned nparams, oc_lds_en;

-   unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+   bool window_space = info->stage == MESA_SHADER_VERTEX ?
+                          info->base.vs.window_space_position : 0;

    bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
 
    pm4 = si_get_shader_pm4_state(shader);
    bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
 
    pm4 = si_get_shader_pm4_state(shader);


@@ -1390,8 +1392,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
    } else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
       vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
 
    } else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
       vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
 

-      if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
-         num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+      if (info->base.vs.blit_sgprs_amd) {
+         num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;

       } else {
          num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
       }
       } else {
          num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
       }


@@ -1701,7 +1703,7 @@ static unsigned si_get_alpha_test_func(struct si_context *sctx)
 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
                                struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
 {
 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
                                struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
 {

-   if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
+   if (!sctx->vertex_elements || vs->info.base.vs.blit_sgprs_amd)

       return;
 
    struct si_vertex_elements *elts = sctx->vertex_elements;
       return;
 
    struct si_vertex_elements *elts = sctx->vertex_elements;


@@ -2611,20 +2613,20 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
    }
 
    sel->num_vs_inputs =
    }
 
    sel->num_vs_inputs =

-      sel->info.stage == MESA_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
+      sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd

          ? sel->info.num_inputs
          : 0;
    sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
 
    /* The prolog is a no-op if there are no inputs. */
    sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&
          ? sel->info.num_inputs
          : 0;
    sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
 
    /* The prolog is a no-op if there are no inputs. */
    sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&

-                          !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+                          !sel->info.base.vs.blit_sgprs_amd;

 
    sel->prim_discard_cs_allowed =
       sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
       !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
       !sel->info.writes_viewport_index &&
 
    sel->prim_discard_cs_allowed =
       sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
       !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
       !sel->info.writes_viewport_index &&

-      !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
+      !sel->info.base.vs.window_space_position && !sel->so.num_outputs;

 
    switch (sel->info.stage) {
    case MESA_SHADER_GEOMETRY:
 
    switch (sel->info.stage) {
    case MESA_SHADER_GEOMETRY:


@@ -2741,8 +2743,9 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
       sel->info.writes_position &&
       !sel->info.writes_viewport_index && /* cull only against viewport 0 */
       !sel->info.writes_memory && !sel->so.num_outputs &&
       sel->info.writes_position &&
       !sel->info.writes_viewport_index && /* cull only against viewport 0 */
       !sel->info.writes_memory && !sel->so.num_outputs &&

-      !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
-      !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+      (sel->info.stage != MESA_SHADER_VERTEX ||
+       (!sel->info.base.vs.blit_sgprs_amd &&
+        !sel->info.base.vs.window_space_position));

 
    /* PA_CL_VS_OUT_CNTL */
    if (sctx->chip_class <= GFX9)
 
    /* PA_CL_VS_OUT_CNTL */
    if (sctx->chip_class <= GFX9)


@@ -2848,8 +2851,8 @@ static void si_update_clip_regs(struct si_context *sctx, struct si_shader_select
 {
    if (next_hw_vs &&
        (!old_hw_vs ||
 {
    if (next_hw_vs &&
        (!old_hw_vs ||

-        old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
-           next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
+        (old_hw_vs->info.stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
+        (next_hw_vs->info.stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||

         old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
         old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
         old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
         old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
         old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
         old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||


@@ -2885,7 +2888,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
 
    sctx->vs_shader.cso = sel;
    sctx->vs_shader.current = sel ? sel->first_variant : NULL;
 
    sctx->vs_shader.cso = sel;
    sctx->vs_shader.current = sel ? sel->first_variant : NULL;

-   sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
+   sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0;

 
    if (si_update_ngg(sctx))
       si_shader_change_notify(sctx);
 
    if (si_update_ngg(sctx))
       si_shader_change_notify(sctx);

diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 5149ee1c643fe70443bae9375590dd9dbc5c74b3..3bf701e314d43e5827875596180c689f1209b6a0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -557,7 +557,7 @@ void si_update_vs_viewport_state(struct si_context *ctx)
       return;
 
    /* When the VS disables clipping and viewport transformation. */
       return;
 
    /* When the VS disables clipping and viewport transformation. */

-   vs_window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+   vs_window_space = info->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;

 
    if (ctx->vs_disables_clipping_viewport != vs_window_space) {
       ctx->vs_disables_clipping_viewport = vs_window_space;
 
    if (ctx->vs_disables_clipping_viewport != vs_window_space) {
       ctx->vs_disables_clipping_viewport = vs_window_space;