radeonsi: enable preemption if the kernel enabled it
authorMarek Olšák <marek.olsak@amd.com>
Thu, 18 Jun 2020 05:07:04 +0000 (01:07 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 22 Jul 2020 16:08:33 +0000 (12:08 -0400)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c

index fbaa7657b2c0e4e6d2563e6c21fc6c294bc07a98..4054e1506a9ceeab95608e7a48d7a46ec2377c68 100644 (file)
@@ -502,6 +502,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        info->has_2d_tiling = true;
        info->has_read_registers_query = true;
        info->has_scheduled_fence_dependency = info->drm_minor >= 28;
        info->has_2d_tiling = true;
        info->has_read_registers_query = true;
        info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+       info->mid_command_buffer_preemption_enabled =
+               amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
 
        info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
        info->num_render_backends = amdinfo->rb_pipes;
 
        info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
        info->num_render_backends = amdinfo->rb_pipes;
@@ -939,6 +941,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
        printf("    has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
        printf("    has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
        printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
        printf("    has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
        printf("    has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
+       printf("    mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
index 6022a199065a6018e18bc719ba1c5b63bd31115c..4b2c35c466cb8ed6cca88e49bb2131f6d00ce9c0 100644 (file)
@@ -152,6 +152,8 @@ struct radeon_info {
        bool                        has_read_registers_query;
        bool                        has_gds_ordered_append;
        bool                        has_scheduled_fence_dependency;
        bool                        has_read_registers_query;
        bool                        has_gds_ordered_append;
        bool                        has_scheduled_fence_dependency;
+       /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
+       bool                        mid_command_buffer_preemption_enabled;
 
        /* Shader cores. */
        uint32_t                    cu_mask[4][2];
 
        /* Shader cores. */
        uint32_t                    cu_mask[4][2];
index 84e4ced02e5e5e69edf514a6d9af16bd3e3ec0b9..bc8f89cacab213ad7e70539f7d93517345b6731a 100644 (file)
@@ -146,7 +146,8 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
 
 void si_init_cp_reg_shadowing(struct si_context *sctx)
 {
 
 void si_init_cp_reg_shadowing(struct si_context *sctx)
 {
-   if (sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
+   if (sctx->screen->info.mid_command_buffer_preemption_enabled ||
+       sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
       sctx->shadowed_regs =
             si_aligned_buffer_create(sctx->b.screen,
                                      SI_RESOURCE_FLAG_UNMAPPABLE,
       sctx->shadowed_regs =
             si_aligned_buffer_create(sctx->b.screen,
                                      SI_RESOURCE_FLAG_UNMAPPABLE,