gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_mode

Oh my god, I wonder what catastrophic issues this was causing on SI.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 625d091fe40d3a8b18f0927f26031e34dfd3a642..b57cc9220709c68ffb505973dabd5e3041c9f9a4 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2442,29 +2442,29 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
                switch (rtex->last_msaa_resolve_target_micro_mode) {
                case 0: /* displayable */
                        switch (rtex->surface.bpe) {
-                       case 8:
+                       case 1:
                             rtex->surface.tiling_index[0] = 10;
                             break;
-                       case 16:
+                       case 2:
                             rtex->surface.tiling_index[0] = 11;
                             break;
-                       default: /* 32, 64 */
+                       default: /* 4, 8 */
                             rtex->surface.tiling_index[0] = 12;
                             break;
                        }
                        break;
                case 1: /* thin */
                        switch (rtex->surface.bpe) {
-                       case 8:
+                       case 1:
                                 rtex->surface.tiling_index[0] = 14;
                                 break;
-                       case 16:
+                       case 2:
                                 rtex->surface.tiling_index[0] = 15;
                                 break;
-                       case 32:
+                       case 4:
                                 rtex->surface.tiling_index[0] = 16;
                                 break;
-                       default: /* 64, 128 */
+                       default: /* 8, 16 */
                                 rtex->surface.tiling_index[0] = 17;
                                 break;
                        }