pan/mdg: Defer smul, vlut until after writeout moves

We can end up with bad dependencies with a depth/stencil export. Let's
let the writeout special cases consume these values if possible, using a
move otherwise in which case it won't be used in the other slots anyway.

total instructions in shared programs: 50508 -> 50507 (<.01%)
instructions in affected programs: 12 -> 11 (-8.33%)
helped: 1
HURT: 0

total bundles in shared programs: 25640 -> 25640 (0.00%)
bundles in affected programs: 0 -> 0
helped: 0
HURT: 0

total quadwords in shared programs: 40899 -> 40899 (0.00%)
quadwords in affected programs: 0 -> 0
helped: 0
HURT: 0

total registers in shared programs: 3917 -> 3916 (-0.03%)
registers in affected programs: 3 -> 2 (-33.33%)
helped: 1
HURT: 0

total threads in shared programs: 2455 -> 2455 (0.00%)
threads in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 168 -> 168 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 186 -> 186 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5513>

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index abaf3ed578e38ccc3b8a4cf8ca865fbd67b2b277..fa9676f3738290a183f03a929fdbbf1c2e7bf310 100644 (file)
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -1004,13 +1004,6 @@ mir_schedule_alu(
                 predicate.no_cond = true;
         }
 
-        if (writeout < PAN_WRITEOUT_Z)
-                mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
-
-        predicate.no_mask = writeout ? (1 << 3) : 0;
-        mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
-        predicate.no_mask = 0;
-
         if (writeout) {
                 /* Propagate up */
                 bundle.last_writeout = branch->last_writeout;
@@ -1103,6 +1096,12 @@ mir_schedule_alu(
                 vlut->unit = UNIT_VLUT;
         }
 
+        mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
+
+        predicate.no_mask = writeout ? (1 << 3) : 0;
+        mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
+        predicate.no_mask = 0;
+
         mir_choose_alu(&vadd, instructions, worklist, len, &predicate, UNIT_VADD);
 
         mir_update_worklist(worklist, len, instructions, vlut);