radv: add support for non-inverted conditional rendering

By default, our internal rendering commands are discarded
only if the predicate is non-zero (ie. DRAW_VISIBLE). But
VK_EXT_conditional_rendering also allows to discard commands
when the predicate is zero, which means we have to use a
different flag.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 136557080d95a288c6576cc8b598d84937957426..d3cd445d97f3297a639d267c6a37d31cbd803ab2 100644 (file)
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -571,7 +571,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
                va += image->dcc_pred_offset;
        }
 
-       si_emit_set_predication_state(cmd_buffer, va);
+       si_emit_set_predication_state(cmd_buffer, true, va);
 }
 
 /**

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 338cb07b3e1e2f0bd9ccde45389a603dc5d8cd87..c697964273dd7f40ab9cce99c8eb9dd2e13e6ebc 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1088,7 +1088,8 @@ void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
                            enum radv_cmd_flush_bits flush_bits,
                            uint64_t gfx9_eop_bug_va);
 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
-void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
+void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
+                                  bool inverted, uint64_t va);
 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
                           uint64_t src_va, uint64_t dest_va,
                           uint64_t size);

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e3c1e2ff7e78f06ecf40b82e7cee6333b086c05e..5b88fdcf3ed16246980fb49b8973b64d6bba9cdf 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1002,12 +1002,23 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 
 /* sets the CP predication state using a boolean stored at va */
 void
-si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
+si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
+                             bool inverted, uint64_t va)
 {
        uint32_t op = 0;
 
-       if (va)
-               op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
+       if (va) {
+               op = PRED_OP(PREDICATION_OP_BOOL64);
+
+               /* By default, our internal rendering commands are discarded
+                * only if the predicate is non-zero (ie. DRAW_VISIBLE). But
+                * VK_EXT_conditional_rendering also allows to discard commands
+                * when the predicate is zero, which means we have to use a
+                * different flag.
+                */
+               op |= inverted ? PREDICATION_DRAW_VISIBLE :
+                                PREDICATION_DRAW_NOT_VISIBLE;
+       }
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
                radeon_emit(cmd_buffer->cs, op);