gallium/radeon: mark shader rings as highest-priority buffers
authorMarek Olšák <marek.olsak@amd.com>
Thu, 11 Aug 2016 20:00:49 +0000 (22:00 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 17 Aug 2016 10:24:35 +0000 (12:24 +0200)
and rename the enum

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/drivers/radeonsi/si_debug.c
src/gallium/drivers/radeonsi/si_descriptors.c

index 463dc1517d9187ad5fd603694adf2d764477470f..76115207d6fa805823d08bca57e38baf58508cb3 100644 (file)
@@ -2280,7 +2280,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
                                state->esgs_ring.buffer_size >> 8);
 
@@ -2290,7 +2290,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
                                state->gsvs_ring.buffer_size >> 8);
        } else {
index 5b470894386e80d77089fca8122422c9f6da5c6c..046573f51703738f3a95f449f91f11b412a23e8b 100644 (file)
@@ -1963,7 +1963,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
                                state->esgs_ring.buffer_size >> 8);
 
@@ -1972,7 +1972,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
                                state->gsvs_ring.buffer_size >> 8);
        } else {
index 72ba830fd35e287fd22ce5b49019c01ec754fa51..e4d669f7e7dbe20a05c2302420ef616b77821c75 100644 (file)
@@ -200,7 +200,6 @@ enum radeon_bo_priority {
     RADEON_PRIO_VERTEX_BUFFER,
 
     RADEON_PRIO_SHADER_RW_BUFFER = 32,
-    RADEON_PRIO_RINGS_STREAMOUT,
     RADEON_PRIO_SCRATCH_BUFFER,
     RADEON_PRIO_COMPUTE_GLOBAL,
 
@@ -220,6 +219,7 @@ enum radeon_bo_priority {
     RADEON_PRIO_CMASK = 60,
     RADEON_PRIO_DCC,
     RADEON_PRIO_HTILE,
+    RADEON_PRIO_SHADER_RINGS,
     /* 63 is the maximum value */
 };
 
index ae11b2c751979b3a7d91cf4aa46194095271dc43..be300ac5b184a226a1f2381227f3c6326c4198a8 100644 (file)
@@ -561,7 +561,6 @@ static const char *priority_to_string(enum radeon_bo_priority priority)
                ITEM(SAMPLER_BUFFER),
                ITEM(VERTEX_BUFFER),
                ITEM(SHADER_RW_BUFFER),
-               ITEM(RINGS_STREAMOUT),
                ITEM(SCRATCH_BUFFER),
                ITEM(COMPUTE_GLOBAL),
                ITEM(SAMPLER_TEXTURE),
@@ -574,6 +573,7 @@ static const char *priority_to_string(enum radeon_bo_priority priority)
                ITEM(CMASK),
                ITEM(DCC),
                ITEM(HTILE),
+               ITEM(SHADER_RINGS),
        };
 #undef ITEM
 
index fcc8a3282bd0866d9053d6f4c2226e68a9476876..f03a8958d15c4b25cfe76b60cba89a20d27f6e6a 100644 (file)
@@ -1772,7 +1772,7 @@ void si_init_all_descriptors(struct si_context *sctx)
        si_init_buffer_resources(&sctx->rw_buffers,
                                 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
                                 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
-                                RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
+                                RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
                                 &ce_offset);
        si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
                            4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);