radeonsi: add support for Sienna Cichlid
authorMarek Olšák <marek.olsak@amd.com>
Fri, 27 Mar 2020 02:08:18 +0000 (22:08 -0400)
committerMarge Bot <eric+marge@anholt.net>
Tue, 9 Jun 2020 16:17:36 +0000 (16:17 +0000)
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>

src/amd/addrlib/src/amdgpu_asic_addr.h
src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
src/amd/common/ac_gpu_info.c
src/amd/common/amd_family.h
src/amd/llvm/ac_llvm_util.c
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c

index 6b598a39df8a98aa2f6a75010c57e883c7688ce8..3307f1941a648ce26236dd605b52d4a6dea3e11c 100644 (file)
@@ -97,6 +97,7 @@
 #define AMDGPU_NAVI10_RANGE     0x01, 0x0A
 #define AMDGPU_NAVI12_RANGE     0x0A, 0x14
 #define AMDGPU_NAVI14_RANGE     0x14, 0x28
+#define AMDGPU_SIENNA_RANGE     0x28, 0x32
 
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
 #define ASICREV_IS_NAVI10_P(r)         ASICREV_IS(r, NAVI10)
 #define ASICREV_IS_NAVI12(r)           ASICREV_IS(r, NAVI12)
 #define ASICREV_IS_NAVI14(r)           ASICREV_IS(r, NAVI14)
+#define ASICREV_IS_SIENNA_M(r)         ASICREV_IS(r, SIENNA)
 
 #endif // _AMDGPU_ASIC_ADDR_H
index eea3deefff830485b3dd476f28eb23a2ba9e6e8d..49f31550c190733a707282d929fdf01120bba17c 100644 (file)
@@ -943,6 +943,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
     {
         case FAMILY_NV:
             m_settings.isDcn2 = 1;
+
+            if (ASICREV_IS_SIENNA_M(chipRevision))
+            {
+                m_settings.supportRbPlus   = 1;
+                m_settings.dccUnsup3DSwDis = 0;
+            }
             break;
         default:
             ADDR_ASSERT(!"Unknown chip family");
index 517de226bd9f75e7e064481df0054d2cae0a5cb6..dbf5c930f4616770600f7d19bf691a2b66423ea0 100644 (file)
@@ -401,6 +401,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                identify_chip(NAVI10);
                identify_chip(NAVI12);
                identify_chip(NAVI14);
+               identify_chip(SIENNA);
                break;
        }
 
@@ -410,7 +411,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                return false;
        }
 
-       if (info->family >= CHIP_NAVI10)
+       if (info->family >= CHIP_SIENNA)
+               info->chip_class = GFX10_3;
+       else if (info->family >= CHIP_NAVI10)
                info->chip_class = GFX10;
        else if (info->family >= CHIP_VEGA10)
                info->chip_class = GFX9;
@@ -712,6 +715,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                case CHIP_RENOIR:
                case CHIP_NAVI10:
                case CHIP_NAVI12:
+               case CHIP_SIENNA:
                        pc_lines = 1024;
                        break;
                case CHIP_NAVI14:
index 8262a3a40b702526a489daffef331033969aacdb..f546c4f96e988bc7d2ffdd8fc56703a76131de46 100644 (file)
@@ -102,6 +102,7 @@ enum radeon_family {
     CHIP_NAVI10,
     CHIP_NAVI12,
     CHIP_NAVI14,
+    CHIP_SIENNA,
     CHIP_LAST,
 };
 
index 5dc4c934ba0ec761074532dc0248bc8d89e5b2de..10a931b150f2fa31beb3d1976a9551488aa5800c 100644 (file)
@@ -157,6 +157,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
                return "gfx1011";
        case CHIP_NAVI14:
                return "gfx1012";
+       case CHIP_SIENNA:
+               return "gfx1030";
        default:
                return "";
        }
index 78816d80d1cd0e763c34b8b9faf7f8dc009101e5..2ef7eaa76420211a37b7638a7e9cf001c0a7ba29 100644 (file)
@@ -63,7 +63,9 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws)
             ws->info.family = i;
             ws->info.name = "GCN-NOOP";
 
-            if (i >= CHIP_NAVI10)
+            if (i >= CHIP_SIENNA)
+               ws->info.chip_class = GFX10_3;
+            else if (i >= CHIP_NAVI10)
                ws->info.chip_class = GFX10;
             else if (i >= CHIP_VEGA10)
                ws->info.chip_class = GFX9;