radv: always pass the GFX9 fence data to si_cs_emit_cache_flush()

Remove two useless checks.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e75080d09757950b7a997fbc003632d444a78f29..2b17fbb339c765cc0c686556e04b5a9bdba21156 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -488,23 +488,16 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
                           enum radv_cmd_flush_bits flags)
 {
        if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
-               uint32_t *ptr = NULL;
-               uint64_t va = 0;
-
                assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
                                RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 
-               if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
-                       va = cmd_buffer->gfx9_fence_va;
-                       ptr = &cmd_buffer->gfx9_fence_idx;
-               }
-
                radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
 
                /* Force wait for graphics or compute engines to be idle. */
                si_cs_emit_cache_flush(cmd_buffer->cs,
                                       cmd_buffer->device->physical_device->rad_info.chip_class,
-                                      ptr, va,
+                                      &cmd_buffer->gfx9_fence_idx,
+                                      cmd_buffer->gfx9_fence_va,
                                       radv_cmd_buffer_uses_mec(cmd_buffer),
                                       flags, cmd_buffer->gfx9_eop_bug_va);
        }

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index f05096fcdfe6ad19eaf24bc7638013dee93ef106..80093ed89edb5f2109ee545b77d103696c157bf6 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -973,15 +973,10 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
        enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
        radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
 
-       uint32_t *ptr = NULL;
-       uint64_t va = 0;
-       if (chip_class == GFX9) {
-               va = cmd_buffer->gfx9_fence_va;
-               ptr = &cmd_buffer->gfx9_fence_idx;
-       }
        si_cs_emit_cache_flush(cmd_buffer->cs,
                               cmd_buffer->device->physical_device->rad_info.chip_class,
-                              ptr, va,
+                              &cmd_buffer->gfx9_fence_idx,
+                              cmd_buffer->gfx9_fence_va,
                               radv_cmd_buffer_uses_mec(cmd_buffer),
                               cmd_buffer->state.flush_bits,
                               cmd_buffer->gfx9_eop_bug_va);