amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not support

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
index 63aabcab096600abfedae7efc9c96c5981d45d4a..cecd15355680757c52be5ea55c5b540082af97b5 100644 (file)
--- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
+++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
@@ -388,10 +388,9 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeDccInfo(
 {
     ADDR_E_RETURNCODE ret = ADDR_OK;
 
-    if (IsLinear(pIn->swizzleMode) || IsBlock256b(pIn->swizzleMode))
+    if (pIn->swizzleMode != ADDR_SW_64KB_Z_X && pIn->swizzleMode != ADDR_SW_64KB_R_X)
     {
-        // Hardware support dcc for 256 swizzle mode, but address lib will not support it because we only
-        // select 256 swizzle mode for small surface, and it's not helpful to enable dcc for small surface.
+        // Hardware does not support DCC for this swizzle mode.
         ret = ADDR_INVALIDPARAMS;
     }
     else if (m_settings.dccUnsup3DSwDis && IsTex3d(pIn->resourceType) && IsDisplaySwizzle(pIn->swizzleMode))