i965: drop brw->is_haswell in favor of devinfo->is_haswell

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 309b33e0ed00120b0fadb137405f52f7be419ae5..e9a4aff093fcbcee86024787384532db52d91012 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -294,7 +294,7 @@ brw_init_driver_functions(struct brw_context *brw,
 
    brwInitFragProgFuncs( functions );
    brw_init_common_queryobj_functions(functions);
-   if (devinfo->gen >= 8 || brw->is_haswell)
+   if (devinfo->gen >= 8 || devinfo->is_haswell)
       hsw_init_queryobj_functions(functions);
    else if (devinfo->gen >= 6)
       gen6_init_queryobj_functions(functions);
@@ -360,7 +360,7 @@ brw_initialize_context_constants(struct brw_context *brw)
    }
 
    unsigned max_samplers =
-      devinfo->gen >= 8 || brw->is_haswell ? BRW_MAX_TEX_UNIT : 16;
+      devinfo->gen >= 8 || devinfo->is_haswell ? BRW_MAX_TEX_UNIT : 16;
 
    ctx->Const.MaxDualSourceDrawBuffers = 1;
    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
@@ -858,7 +858,6 @@ brwCreateContext(gl_api api,
    brw->screen = screen;
    brw->bufmgr = screen->bufmgr;
 
-   brw->is_haswell = devinfo->is_haswell;
    brw->is_cherryview = devinfo->is_cherryview;
    brw->is_broxton = devinfo->is_broxton || devinfo->is_geminilake;
    brw->has_llc = devinfo->has_llc;

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 41c31e8cdad4c28f8d542bbacfbf197938fbdf3a..5d44dac5414b374cd2daabe8387ad9291722fddd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -746,7 +746,6 @@ struct brw_context
 
    uint64_t max_gtt_map_object_size;
 
-   bool is_haswell;
    bool is_cherryview;
    bool is_broxton;
 

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index cc564a012b6d515f99012773b6f409413cbfdd6a..cf72889b411a0f336061465419d90b4be9b71cf4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -155,7 +155,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
     * number of threads per subslice.
     */
    const unsigned scratch_ids_per_subslice =
-      brw->is_haswell ? 16 * 8 : devinfo->max_cs_threads;
+      devinfo->is_haswell ? 16 * 8 : devinfo->max_cs_threads;
 
    brw_alloc_stage_scratch(brw, &brw->cs.base,
                            prog_data.base.total_scratch,

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 86f9e5bf7d8667a18d664f4550dc85837554168b..d1ec2e3f09d7b68006b4e48de3b7de60b5e74c77 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -296,7 +296,7 @@ brw_merge_inputs(struct brw_context *brw,
       brw->vb.inputs[i].glarray = arrays[i];
    }
 
-   if (devinfo->gen < 8 && !brw->is_haswell) {
+   if (devinfo->gen < 8 && !devinfo->is_haswell) {
       uint64_t mask = ctx->VertexProgram._Current->info.inputs_read;
       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 1363c5591a5cd7d946d8617b11db182764dd71f6..9b81999ea05430b2a3cf91edb16f7b98da3a7b44 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -254,7 +254,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
    int size = glarray->Size;
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const bool is_ivybridge_or_older =
-      devinfo->gen <= 7 && !devinfo->is_baytrail && !brw->is_haswell;
+      devinfo->gen <= 7 && !devinfo->is_baytrail && !devinfo->is_haswell;
 
    if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
       fprintf(stderr, "type %s size %d normalized %d\n",
@@ -315,7 +315,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
             return ubyte_types_norm[size];
          }
       case GL_FIXED:
-         if (devinfo->gen >= 8 || brw->is_haswell)
+         if (devinfo->gen >= 8 || devinfo->is_haswell)
             return fixed_point_types[size];
 
          /* This produces GL_FIXED inputs as values between INT32_MIN and
@@ -329,7 +329,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
        */
       case GL_INT_2_10_10_10_REV:
          assert(size == 4);
-         if (devinfo->gen >= 8 || brw->is_haswell) {
+         if (devinfo->gen >= 8 || devinfo->is_haswell) {
             return glarray->Format == GL_BGRA
                ? ISL_FORMAT_B10G10R10A2_SNORM
                : ISL_FORMAT_R10G10B10A2_SNORM;
@@ -337,7 +337,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
          return ISL_FORMAT_R10G10B10A2_UINT;
       case GL_UNSIGNED_INT_2_10_10_10_REV:
          assert(size == 4);
-         if (devinfo->gen >= 8 || brw->is_haswell) {
+         if (devinfo->gen >= 8 || devinfo->is_haswell) {
             return glarray->Format == GL_BGRA
                ? ISL_FORMAT_B10G10R10A2_UNORM
                : ISL_FORMAT_R10G10B10A2_UNORM;
@@ -354,7 +354,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
        */
       if (glarray->Type == GL_INT_2_10_10_10_REV) {
          assert(size == 4);
-         if (devinfo->gen >= 8 || brw->is_haswell) {
+         if (devinfo->gen >= 8 || devinfo->is_haswell) {
             return glarray->Format == GL_BGRA
                ? ISL_FORMAT_B10G10R10A2_SSCALED
                : ISL_FORMAT_R10G10B10A2_SSCALED;
@@ -362,7 +362,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
          return ISL_FORMAT_R10G10B10A2_UINT;
       } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
          assert(size == 4);
-         if (devinfo->gen >= 8 || brw->is_haswell) {
+         if (devinfo->gen >= 8 || devinfo->is_haswell) {
             return glarray->Format == GL_BGRA
                ? ISL_FORMAT_B10G10R10A2_USCALED
                : ISL_FORMAT_R10G10B10A2_USCALED;
@@ -386,7 +386,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
       case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
       case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
       case GL_FIXED:
-         if (devinfo->gen >= 8 || brw->is_haswell)
+         if (devinfo->gen >= 8 || devinfo->is_haswell)
             return fixed_point_types[size];
 
          /* This produces GL_FIXED inputs as values between INT32_MIN and

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index f800c4c80c7e8bb046725073e6a8eaf2482be3ba..bd36fa39c4d2b93d543301aff05ec4a15494662a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -492,7 +492,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
              (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
    ADVANCE_BATCH();
 
-   if (devinfo->gen == 7 && !brw->is_haswell &&
+   if (devinfo->gen == 7 && !devinfo->is_haswell &&
        pipeline == BRW_RENDER_PIPELINE) {
       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
        * PIPELINE_SELECT [DevBWR+]":

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index a341408fe06109b7195a5ec640ccf539f5287053..063b814b9a3a78e0b5e3315dec59aea06a4b3509 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -73,7 +73,7 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
-   if (devinfo->gen == 7 && !brw->is_haswell) {
+   if (devinfo->gen == 7 && !devinfo->is_haswell) {
       if (flags & PIPE_CONTROL_CS_STALL) {
          /* If we're doing a CS stall, reset the counter and carry on. */
          brw->pipe_controls_since_last_cs_stall = 0;
@@ -383,7 +383,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
                                   PIPE_CONTROL_WRITE_IMMEDIATE,
                                   brw->workaround_bo, 0, 0);
 
-      if (brw->is_haswell) {
+      if (devinfo->is_haswell) {
          /* Haswell needs addition work-arounds:
           *
           * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":

diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 39ca5e869ae4de43dcec1c9773d855ba8b7bb1a8..3b696aa9cbc3f5b0d6bda8cb878cf5171821d423 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -83,7 +83,7 @@ can_cut_index_handle_prims(struct gl_context *ctx,
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    /* Otherwise Haswell can do it all. */
-   if (devinfo->gen >= 8 || brw->is_haswell)
+   if (devinfo->gen >= 8 || devinfo->is_haswell)
       return true;
 
    if (!can_cut_index_handle_restart_index(ctx, ib)) {

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index db4da8cae2b6aafb02cd0e1c6d282143681b52d3..9303dc85b9e5fea4f75c9784fc669922daad581b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -292,7 +292,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
    /* Typed surface messages are handled by the render cache on IVB, so we
     * need to flush it too.
     */
-   if (devinfo->gen == 7 && !brw->is_haswell)
+   if (devinfo->gen == 7 && !devinfo->is_haswell)
       bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
 
    brw_emit_pipe_control_flush(brw, bits);
@@ -647,7 +647,7 @@ brw_setup_tex_for_precompile(struct brw_context *brw,
                              struct gl_program *prog)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   const bool has_shader_channel_select = brw->is_haswell || devinfo->gen >= 8;
+   const bool has_shader_channel_select = devinfo->is_haswell || devinfo->gen >= 8;
    unsigned sampler_count = util_last_bit(prog->SamplersUsed);
    for (unsigned i = 0; i < sampler_count; i++) {
       if (!has_shader_channel_select && (prog->ShadowSamplers & (1 << i))) {

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 1d15f67b5ebf4bcfea2a5af431d53c88d6d321dc..e14ef4941d796fde1707c143937bccebc5f5b20d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -180,7 +180,7 @@ void brw_init_state( struct brw_context *brw )
       gen9_init_atoms(brw);
    else if (devinfo->gen >= 8)
       gen8_init_atoms(brw);
-   else if (brw->is_haswell)
+   else if (devinfo->is_haswell)
       gen75_init_atoms(brw);
    else if (devinfo->gen >= 7)
       gen7_init_atoms(brw);

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index a2f79a66ef9992502c907ab85661671d7d340a89..38af5131595353bddc454ed45ab4b6ad5975c21b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -345,7 +345,7 @@ brw_vs_populate_key(struct brw_context *brw,
    brw_populate_sampler_prog_key_data(ctx, prog, &key->tex);
 
    /* BRW_NEW_VS_ATTRIB_WORKAROUNDS */
-   if (devinfo->gen < 8 && !brw->is_haswell) {
+   if (devinfo->gen < 8 && !devinfo->is_haswell) {
       memcpy(key->gl_attrib_wa_flags, brw->vb.attrib_wa_flags,
              sizeof(brw->vb.attrib_wa_flags));
    }

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index fdeb83fe6dda139613fc93663c53476b686e62c0..92354e464ca672189387e201dcac44f72ce774d7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -330,7 +330,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
          /* Haswell handles texture swizzling as surface format overrides
           * (except for GL_ALPHA); all other platforms need MOVs in the shader.
           */
-         if (alpha_depth || (devinfo->gen < 8 && !brw->is_haswell))
+         if (alpha_depth || (devinfo->gen < 8 && !devinfo->is_haswell))
             key->swizzles[s] = brw_get_texture_swizzle(ctx, t);
 
          if (devinfo->gen < 8 &&
@@ -359,7 +359,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
                 * leaving normal texture swizzling to SCS.
                 */
                unsigned src_swizzle =
-                  brw->is_haswell ? t->_Swizzle : key->swizzles[s];
+                  devinfo->is_haswell ? t->_Swizzle : key->swizzles[s];
                for (int i = 0; i < 4; i++) {
                   unsigned src_comp = GET_SWZ(src_swizzle, i);
                   if (src_comp == SWIZZLE_ONE || src_comp == SWIZZLE_W) {
@@ -374,7 +374,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
                 * request blue.  Haswell can use SCS for this, but Ivybridge
                 * needs a shader workaround.
                 */
-               if (!brw->is_haswell)
+               if (!devinfo->is_haswell)
                   key->gather_channel_quirk_mask |= 1 << s;
                break;
             }

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 367bde3a0beb684729fef3e0fb5c54e5bc8c25d0..f9628e928a4941a33f2c47df4741e2ae16ec4513 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -509,7 +509,7 @@ brw_update_texture_surface(struct gl_context *ctx,
                                    format == ISL_FORMAT_R32G32_SINT ||
                                    format == ISL_FORMAT_R32G32_UINT)) {
             format = ISL_FORMAT_R32G32_FLOAT_LD;
-            need_green_to_blue = brw->is_haswell;
+            need_green_to_blue = devinfo->is_haswell;
          } else if (devinfo->gen == 6) {
             /* Sandybridge's gather4 message is broken for integer formats.
              * To work around this, we pretend the surface is UNORM for

diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 46813826eb6006f911a55b3af560aba60bc95423..72f00d564043e296c72a9cc28f61b2aa09c485f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -65,7 +65,7 @@ gen6_upload_push_constants(struct brw_context *brw,
       int i;
       const int size = prog_data->nr_params * sizeof(gl_constant_value);
       gl_constant_value *param;
-      if (devinfo->gen >= 8 || brw->is_haswell) {
+      if (devinfo->gen >= 8 || devinfo->is_haswell) {
          param = intel_upload_space(brw, size, 32,
                                     &stage_state->push_const_bo,
                                     &stage_state->push_const_offset);

diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 357f041d3f594db646346e71105e463adc95011f..b43ca0ee478e7cfcbf37e669edab984913912b7a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -297,7 +297,7 @@ gen6_queryobj_get_results(struct gl_context *ctx,
        * and correctly emitted the number of pixel shader invocations, but,
        * whomever forgot to undo the multiply by 4.
        */
-      if (devinfo->gen == 8 || brw->is_haswell)
+      if (devinfo->gen == 8 || devinfo->is_haswell)
          query->Base.Result /= 4;
       break;
 

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index ac283e7374f248d676fe40bcc665e6b3fe904cbc..a368af3631647d3ec02691b318a2f0687b31bd06 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -153,7 +153,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
 
       /* Demote any clients with no ways assigned to LLC. */
       OUT_BATCH(GEN7_L3SQCREG1);
-      OUT_BATCH((brw->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
+      OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
                  devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
                 (has_dc ? 0 : GEN7_L3SQCREG1_CONV_DC_UC) |

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 9d51a40166817a725a83c60e73b0fb4bac900153..58f0a1bdbfd6af8f137bcb6067188a02e5abded3 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -39,6 +39,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
                             uint32_t width, uint32_t height,
                             uint32_t tile_x, uint32_t tile_y)
 {
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    const uint8_t mocs = GEN7_MOCS_L3;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
@@ -161,7 +162,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       ADVANCE_BATCH();
    } else {
       stencil_mt->r8stencil_needs_update = true;
-      const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
+      const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index f498c291688dd56724dcce8da5090679fc3cbe78..44ce2c6a58e4584a0cd4b8d0c5fcd0c62d99832f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -72,7 +72,7 @@ gen7_allocate_push_constants(struct brw_context *brw)
 
    unsigned avail_size = 16;
    unsigned multiplier =
-      (devinfo->gen >= 8 || (brw->is_haswell && devinfo->gt == 3)) ? 2 : 1;
+      (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 2 : 1;
 
    int stages = 2 + gs_present + 2 * tess_present;
 
@@ -146,7 +146,7 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
     *
     * No such restriction exists for Haswell or Baytrail.
     */
-   if (devinfo->gen < 8 && !brw->is_haswell && !devinfo->is_baytrail)
+   if (devinfo->gen < 8 && !devinfo->is_haswell && !devinfo->is_baytrail)
       gen7_emit_cs_stall_flush(brw);
 }
 
@@ -181,7 +181,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const int push_size_kB =
-      (devinfo->gen >= 8 || (brw->is_haswell && devinfo->gt == 3)) ? 32 : 16;
+      (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 32 : 16;
 
    /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */
    struct brw_vue_prog_data *prog_data[4] = {
@@ -224,7 +224,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
    gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size,
                       tess_present, gs_present, entry_size, entries, start);
 
-   if (devinfo->gen == 7 && !brw->is_haswell && !devinfo->is_baytrail)
+   if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
       gen7_emit_vs_workaround_flush(brw);
 
    BEGIN_BATCH(8);

diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index fde0bce715200d6602d254cecfc07c8bbc71015c..24f52a7d752ed37ac48f59c6d650c5b8e8f487c8 100644 (file)
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -339,7 +339,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
        * and correctly emitted the number of pixel shader invocations, but,
        * whomever forgot to undo the multiply by 4.
        */
-      if (devinfo->gen == 8 || brw->is_haswell)
+      if (devinfo->gen == 8 || devinfo->is_haswell)
          shr_gpr0_by_2_bits(brw);
       break;
    case GL_TIME_ELAPSED:

diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c
index c14efd571d617f89fa2f1ce83e0a5ced3e7300d3..f84063ded0478ae4530ce8f40f41f2e520018cc5 100644 (file)
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -196,8 +196,9 @@ hsw_pause_transform_feedback(struct gl_context *ctx,
    struct brw_context *brw = brw_context(ctx);
    struct brw_transform_feedback_object *brw_obj =
       (struct brw_transform_feedback_object *) obj;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
-   if (brw->is_haswell) {
+   if (devinfo->is_haswell) {
       /* Flush any drawing so that the counters have the right values. */
       brw_emit_mi_flush(brw);
 
@@ -225,8 +226,9 @@ hsw_resume_transform_feedback(struct gl_context *ctx,
    struct brw_context *brw = brw_context(ctx);
    struct brw_transform_feedback_object *brw_obj =
       (struct brw_transform_feedback_object *) obj;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
-   if (brw->is_haswell) {
+   if (devinfo->is_haswell) {
       /* Reload the SOL buffer offset registers. */
       for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
          BEGIN_BATCH(3);

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index fddb96016b6f1684fb35df910beccbadfde2cd9d..c7d7029fbd0e1bd926b7241dc55c78c6820586c1 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -506,7 +506,7 @@ brw_finish_batch(struct brw_context *brw)
       if (devinfo->gen >= 7)
          gen7_restore_default_l3_config(brw);
 
-      if (brw->is_haswell) {
+      if (devinfo->is_haswell) {
          /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
           * 3DSTATE_CC_STATE_POINTERS > "Note":
           *
@@ -999,7 +999,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
-   assert(devinfo->gen >= 8 || brw->is_haswell);
+   assert(devinfo->gen >= 8 || devinfo->is_haswell);
 
    BEGIN_BATCH(3);
    OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
@@ -1016,7 +1016,7 @@ brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
 {
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
-   assert(devinfo->gen >= 8 || brw->is_haswell);
+   assert(devinfo->gen >= 8 || devinfo->is_haswell);
 
    BEGIN_BATCH(6);
    OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index c9411f598ac6b47b8c83b40d23043da72e9ff270..13253d00fc3d7f7376162d9979caa03e47cc77bc 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -138,7 +138,7 @@ intelInitExtensions(struct gl_context *ctx)
 
    if (devinfo->gen >= 8)
       ctx->Const.GLSLVersion = 450;
-   else if (brw->is_haswell && can_do_pipelined_register_writes(brw->screen))
+   else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen))
       ctx->Const.GLSLVersion = 450;
    else if (devinfo->gen >= 7 && can_do_pipelined_register_writes(brw->screen))
       ctx->Const.GLSLVersion = 420;
@@ -239,7 +239,7 @@ intelInitExtensions(struct gl_context *ctx)
              ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
             ctx->Extensions.ARB_compute_shader = true;
             ctx->Extensions.ARB_ES3_1_compatibility =
-               devinfo->gen >= 8 || brw->is_haswell;
+               devinfo->gen >= 8 || devinfo->is_haswell;
          }
 
          if (can_do_predicate_writes(brw->screen))
@@ -247,7 +247,7 @@ intelInitExtensions(struct gl_context *ctx)
       }
    }
 
-   if (devinfo->gen >= 8 || brw->is_haswell) {
+   if (devinfo->gen >= 8 || devinfo->is_haswell) {
       ctx->Extensions.ARB_stencil_texturing = true;
       ctx->Extensions.ARB_texture_stencil8 = true;
       ctx->Extensions.OES_geometry_shader = true;
@@ -255,7 +255,7 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.OES_viewport_array = true;
    }
 
-   if (devinfo->gen >= 8 || brw->is_haswell || devinfo->is_baytrail) {
+   if (devinfo->gen >= 8 || devinfo->is_haswell || devinfo->is_baytrail) {
       ctx->Extensions.ARB_robust_buffer_access_behavior = true;
    }
 

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 742f35c4a64cb122c4d7fd1774005cd247702d89..ed18d2a8230822b1cfe955d80884df36c4ee6e99 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1793,7 +1793,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
    assert(mt->hiz_buf);
    assert(mt->surf.size > 0);
 
-   if (devinfo->gen >= 8 || brw->is_haswell) {
+   if (devinfo->gen >= 8 || devinfo->is_haswell) {
       uint32_t width = minify(mt->surf.phys_level0_sa.width, level);
       uint32_t height = minify(mt->surf.phys_level0_sa.height, level);