ac/radeonsi: add tcs_rel_ids to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8dc1d903e0a012aaa92c2e250dc4168e7f459016..bdbe6f82e22922d7a45502d29a8b3d2b3189b44b 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -111,7 +111,6 @@ struct nir_to_llvm_context {
        LLVMValueRef oc_lds;
        LLVMValueRef merged_wave_info;
        LLVMValueRef tess_factor_offset;
-       LLVMValueRef tcs_rel_ids;
        LLVMValueRef tes_rel_patch_id;
        LLVMValueRef tes_u;
        LLVMValueRef tes_v;
@@ -402,7 +401,7 @@ static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
 {
        switch (ctx->stage) {
        case MESA_SHADER_TESS_CTRL:
-               return unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
+               return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
        case MESA_SHADER_TESS_EVAL:
                return ctx->tes_rel_patch_id;
                break;
@@ -850,7 +849,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
                        add_arg(&args, ARG_VGPR, ctx->ac.i32,
                                &ctx->abi.tcs_patch_id);
                        add_arg(&args, ARG_VGPR, ctx->ac.i32,
-                               &ctx->tcs_rel_ids);
+                               &ctx->abi.tcs_rel_ids);
 
                        declare_vs_input_vgprs(ctx, &args);
                } else {
@@ -878,7 +877,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
                        add_arg(&args, ARG_VGPR, ctx->ac.i32,
                                &ctx->abi.tcs_patch_id);
                        add_arg(&args, ARG_VGPR, ctx->ac.i32,
-                               &ctx->tcs_rel_ids);
+                               &ctx->abi.tcs_rel_ids);
                }
                break;
        case MESA_SHADER_TESS_EVAL:
@@ -4207,7 +4206,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
                break;
        case nir_intrinsic_load_invocation_id:
                if (ctx->stage == MESA_SHADER_TESS_CTRL)
-                       result = unpack_param(&ctx->ac, ctx->nctx->tcs_rel_ids, 8, 5);
+                       result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
                else
                        result = ctx->abi->gs_invocation_id;
                break;
@@ -6149,8 +6148,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
 {
        unsigned stride, outer_comps, inner_comps;
        struct ac_build_if_state if_ctx, inner_if_ctx;
-       LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 8, 5);
-       LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->tcs_rel_ids, 0, 8);
+       LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
+       LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
        unsigned tess_inner_index, tess_outer_index;
        LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
        LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
@@ -6539,7 +6538,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
                                              ctx->ac.i32_0, "");
        ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
        ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
-       ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
+       ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
        ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
 }
 

diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 6f526d9f254d18b9b0414f63cfab3d250fde8376..d5d7c9c3272d12d89b4aa91910d523f0b2b32a1e 100644 (file)
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -43,6 +43,7 @@ struct ac_shader_abi {
        LLVMValueRef vertex_id;
        LLVMValueRef instance_id;
        LLVMValueRef tcs_patch_id;
+       LLVMValueRef tcs_rel_ids;
        LLVMValueRef tes_patch_id;
        LLVMValueRef gs_prim_id;
        LLVMValueRef gs_invocation_id;

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index dc7f12ce6a8e24cfb08bc82a646f60ac9d29ee05..5945c3e506f4abb3eb3c13b105c6e192f3eb759e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -274,7 +274,7 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
 {
        switch (ctx->type) {
        case PIPE_SHADER_TESS_CTRL:
-               return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
+               return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
 
        case PIPE_SHADER_TESS_EVAL:
                return LLVMGetParam(ctx->main_fn,
@@ -1946,7 +1946,7 @@ void si_load_system_value(struct si_shader_context *ctx,
 
        case TGSI_SEMANTIC_INVOCATIONID:
                if (ctx->type == PIPE_SHADER_TESS_CTRL)
-                       value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
+                       value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
                else if (ctx->type == PIPE_SHADER_GEOMETRY)
                        value = ctx->abi.gs_invocation_id;
                else
@@ -2995,7 +2995,7 @@ static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
        LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
        uint64_t inputs;
 
-       invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
+       invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
        buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
        buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
 
@@ -3248,7 +3248,7 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
        si_copy_tcs_inputs(bld_base);
 
        rel_patch_id = get_rel_patch_id(ctx);
-       invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
+       invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
        tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
 
        if (ctx->screen->info.chip_class >= GFX9) {
@@ -3309,7 +3309,7 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
        tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
 
        /* Leave a hole corresponding to the two input VGPRs. This ensures that
-        * the invocation_id output does not alias the param_tcs_rel_ids input,
+        * the invocation_id output does not alias the tcs_rel_ids input,
         * which saves a V_MOV on gfx9.
         */
        vgpr += 2;
@@ -3370,8 +3370,9 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
        ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
                                   ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
                                   vgpr++, "");
-       ret = si_insert_input_ret_float(ctx, ret,
-                                       ctx->param_tcs_rel_ids, vgpr++);
+       ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
+                                  ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
+                                  vgpr++, "");
        ctx->return_value = ret;
 }
 
@@ -4667,7 +4668,7 @@ static void create_function(struct si_shader_context *ctx)
 
                /* VGPRs */
                add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
-               ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
+               add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
 
                /* param_tcs_offchip_offset and param_tcs_factor_offset are
                 * placed after the user SGPRs.
@@ -4706,7 +4707,7 @@ static void create_function(struct si_shader_context *ctx)
 
                /* VGPRs (first TCS, then VS) */
                add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
-               ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
+               add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
 
                if (ctx->type == PIPE_SHADER_VERTEX) {
                        declare_vs_input_vgprs(ctx, &fninfo,

diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 4a51958676af101118aac58d12464696dd95c8a1..6b4acc51f9c496c6996fc93656e320e255af1a8d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -169,7 +169,6 @@ struct si_shader_context {
        int param_tcs_factor_addr_base64k;
        int param_tcs_offchip_offset;
        int param_tcs_factor_offset;
-       int param_tcs_rel_ids;
 
        /* API TES */
        int param_tes_u;