ac,radeonsi: replace == GFX10 with >= GFX10 where it's needed

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index cfdba201d4d421f4ba905e22897479e6100a56b0..3e0f70d084d9cd053baa102f4f46e2b5e1eaf47d 100644 (file)
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -4043,7 +4043,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
        case nir_intrinsic_shuffle:
                if (ctx->ac.chip_class == GFX8 ||
                    ctx->ac.chip_class == GFX9 ||
        case nir_intrinsic_shuffle:
                if (ctx->ac.chip_class == GFX8 ||
                    ctx->ac.chip_class == GFX9 ||

-                   (ctx->ac.chip_class == GFX10 && ctx->ac.wave_size == 32)) {
+                   (ctx->ac.chip_class >= GFX10 && ctx->ac.wave_size == 32)) {

                        result = ac_build_shuffle(&ctx->ac, get_src(ctx, instr->src[0]),
                                                  get_src(ctx, instr->src[1]));
                } else {
                        result = ac_build_shuffle(&ctx->ac, get_src(ctx, instr->src[0]),
                                                  get_src(ctx, instr->src[1]));
                } else {

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index df3b53aaec2d1190db592775c645a7e6b1eca3b3..ecce673caf295bdd1d2229fd2383f990cc23f197 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4745,8 +4745,9 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
        * into account would complicate the fast path (where everything
        * is nicely aligned).
        */
        * into account would complicate the fast path (where everything
        * is nicely aligned).
        */

-      bool check_alignment = log_hw_load_size >= 1 && (sscreen->info.chip_class == GFX6 ||
-                                                       sscreen->info.chip_class == GFX10);
+      bool check_alignment =
+            log_hw_load_size >= 1 &&
+            (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class >= GFX10);

       bool opencode = sscreen->options.vs_fetch_always_opencode;
 
       if (check_alignment && (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
       bool opencode = sscreen->options.vs_fetch_always_opencode;
 
       if (check_alignment && (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 6cb0dbf0490e9ed5b859634312038a71a9038262..0fd1714f8f83ebcdca22586f4d64e1d0d3a2b59d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1312,11 +1312,12 @@ static void si_emit_shader_vs(struct si_context *sctx)
                                  shader->vgt_vertex_reuse_block_cntl);
 
    /* Required programming for tessellation. (legacy pipeline only) */
                                  shader->vgt_vertex_reuse_block_cntl);
 
    /* Required programming for tessellation. (legacy pipeline only) */

-   if (sctx->chip_class == GFX10 && shader->selector->type == PIPE_SHADER_TESS_EVAL) {
-      radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
+   if (sctx->chip_class >= GFX10 && shader->selector->type == PIPE_SHADER_TESS_EVAL) {
+      radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
+                                 SI_TRACKED_VGT_GS_ONCHIP_CNTL,

                                  S_028A44_ES_VERTS_PER_SUBGRP(250) |
                                  S_028A44_ES_VERTS_PER_SUBGRP(250) |

-                                    S_028A44_GS_PRIMS_PER_SUBGRP(126) |
-                                    S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
+                                 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
+                                 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));

    }
 
    if (sctx->chip_class >= GFX10) {
    }
 
    if (sctx->chip_class >= GFX10) {


@@ -2651,7 +2652,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
          u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
 
       /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
          u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
 
       /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */

-      sel->tess_turns_off_ngg = sscreen->info.chip_class == GFX10 &&
+      sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&

                                 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
       break;
 
                                 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
       break;
 


@@ -2748,7 +2749,8 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
    }
 
    sel->ngg_culling_allowed =
    }
 
    sel->ngg_culling_allowed =

-      sscreen->info.chip_class == GFX10 && sscreen->info.has_dedicated_vram &&
+      sscreen->info.chip_class >= GFX10 &&
+      sscreen->info.has_dedicated_vram &&

       sscreen->use_ngg_culling &&
       /* Disallow TES by default, because TessMark results are mixed. */
       (sel->type == PIPE_SHADER_VERTEX ||
       sscreen->use_ngg_culling &&
       /* Disallow TES by default, because TessMark results are mixed. */
       (sel->type == PIPE_SHADER_VERTEX ||