radeonsi: move the tess factor ring size assertion to a place where it matters
authorMarek Olšák <marek.olsak@amd.com>
Fri, 2 Aug 2019 20:26:21 +0000 (16:26 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 19 Aug 2019 21:23:38 +0000 (17:23 -0400)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_state_shaders.c

index 139f4954dfa0f38832a4906ca2894adc949c36ea..6d9cce2619b6ce841d4bcc9ddc6b58037adf1b20 100644 (file)
@@ -1088,7 +1088,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
        }
 
        sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
-       assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
        sscreen->tess_offchip_ring_size = max_offchip_buffers *
                                          sscreen->tess_offchip_block_dw_size * 4;
 
index 65035f0e256dda6549a05e0288ad45b9c87f9aff..032d7a09cc4c4a00dcbf311a37c9de8c5e1a7a15 100644 (file)
@@ -3725,6 +3725,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
        assert(!sctx->tess_rings);
+       assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
 
        /* The address must be aligned to 2^19, because the shader only
         * receives the high 13 bits.