radeonsi: add support for Renoir

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h
index 9306fcce57de51df7cbe039bc2c6ad5c45751870..fc545a1af0c75a4a6e5b9485acd9a8304911f56b 100644 (file)
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -254,6 +254,8 @@ CHIPSET(0x66AF, VEGA20)
 CHIPSET(0x15DD, RAVEN)
 CHIPSET(0x15D8, RAVEN)
 
+CHIPSET(0x1636, RENOIR)
+
 CHIPSET(0x738C, ARCTURUS)
 CHIPSET(0x7388, ARCTURUS)
 CHIPSET(0x738E, ARCTURUS)

diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h
index 75c06796ad7f01ade49ed1a9d7c667388627f789..0358ab127b288874aebac15483f5ab633b2454d2 100644 (file)
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -93,6 +93,7 @@
 
 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
 #define AMDGPU_RAVEN2_RANGE     0x81, 0xFF
+#define AMDGPU_RENOIR_RANGE     0x01, 0x91
 
 #define AMDGPU_ARCTURUS_RANGE   0x32, 0xFF
 
@@ -141,6 +142,7 @@
 
 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
 #define ASICREV_IS_RAVEN2(r)           ASICREV_IS(r, RAVEN2)
+#define ASICREV_IS_RENOIR(r)           ASICREV_IS(r, RENOIR)
 
 #define ASICREV_IS_ARCTURUS(r)         ASICREV_IS(r, ARCTURUS)
 

diff --git a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
index 611c18fc1f0514140d6e40ae96d8fc29700ac18a..cb0d3f054d715fc77acd4f77e26bee7df96f8887 100644 (file)
--- a/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
@@ -1312,6 +1312,11 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
                 m_settings.applyAliasFix = 1;
             }
 
+            if (ASICREV_IS_RENOIR(uChipRevision))
+            {
+                m_settings.isRaven = 1;
+            }
+
             m_settings.isDcn1 = m_settings.isRaven;
 
             m_settings.metaBaseAlignFix = 1;

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index b02a3e98113e6389f4cef5e5aaf419eb40d3c853..9ec7359ed79abde45e30070b485bd827695cff56 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -478,7 +478,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 
        if (info->drm_minor >= 31 &&
            (info->family == CHIP_RAVEN ||
-            info->family == CHIP_RAVEN2)) {
+            info->family == CHIP_RAVEN2 ||
+            info->family == CHIP_RENOIR)) {
                if (info->num_render_backends == 1)
                        info->use_display_dcc_unaligned = true;
                else

diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index b43224b3b7355d18039dc8a7b2278e8b4008a629..a201f2d1fc5eeb3d22419c0b520a50f53b5fc79a 100644 (file)
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -132,6 +132,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
        case CHIP_VEGA20:
                return "gfx906";
        case CHIP_RAVEN2:
+       case CHIP_RENOIR:
                return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
        case CHIP_ARCTURUS:
                return "gfx908";

diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 1d6578c0ef761e1d67dfcd94f614e57831483206..2386eecb5d40e51caf19d70e51b5e9e26d26c109 100644 (file)
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -97,6 +97,7 @@ enum radeon_family {
     CHIP_VEGA20,
     CHIP_RAVEN,
     CHIP_RAVEN2,
+    CHIP_RENOIR,
     CHIP_ARCTURUS,
     CHIP_NAVI10,
     CHIP_NAVI12,

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index f19c2a22ebd362322979b2965ab82bf254fd3afd..139f4954dfa0f38832a4906ca2894adc949c36ea 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1150,6 +1150,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
        sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
                                        sscreen->info.family == CHIP_RAVEN;
        sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
+                                          sscreen->info.family == CHIP_RENOIR ||
                                           sscreen->info.chip_class >= GFX10;
        sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
        sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
@@ -1195,7 +1196,8 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                        (sscreen->info.family == CHIP_STONEY ||
                         sscreen->info.family == CHIP_VEGA12 ||
                         sscreen->info.family == CHIP_RAVEN ||
-                        sscreen->info.family == CHIP_RAVEN2);
+                        sscreen->info.family == CHIP_RAVEN2 ||
+                        sscreen->info.family == CHIP_RENOIR);
        }
 
        sscreen->dcc_msaa_allowed =

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 5cdad02469407399b22589ac8f8cd8f9540b1082..19e568259c279bb343b7e0f509f8de41bdccc8e7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5685,6 +5685,7 @@ static void si_init_config(struct si_context *sctx)
                        break;
                case CHIP_RAVEN:
                case CHIP_RAVEN2:
+               case CHIP_RENOIR:
                case CHIP_NAVI10:
                case CHIP_NAVI12:
                        pc_lines = 1024;