amd: add support for Navy Flounder

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>

diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h
index 5f7d797f2c8b92d5a32d555606d29663045923b7..bef2ef78575ca79d7ffa9abe63610c8db55cce43 100644 (file)
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -98,6 +98,7 @@
 #define AMDGPU_NAVI12_RANGE     0x0A, 0x14
 #define AMDGPU_NAVI14_RANGE     0x14, 0x28
 #define AMDGPU_SIENNA_CICHLID_RANGE     0x28, 0x32
+#define AMDGPU_NAVY_FLOUNDER_RANGE      0x32, 0x3C
 
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@@ -146,5 +147,6 @@
 #define ASICREV_IS_NAVI12(r)           ASICREV_IS(r, NAVI12)
 #define ASICREV_IS_NAVI14(r)           ASICREV_IS(r, NAVI14)
 #define ASICREV_IS_SIENNA_CICHLID(r)   ASICREV_IS(r, SIENNA_CICHLID)
+#define ASICREV_IS_NAVY_FLOUNDER(r)    ASICREV_IS(r, NAVY_FLOUNDER)
 
 #endif // _AMDGPU_ASIC_ADDR_H

diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
index 2050cf4b150c60b750caf52b1533ff0615028d4f..8116c3b169cd421e7a809d886b02ef923a52404c 100644 (file)
--- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
+++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
@@ -927,6 +927,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
                 m_settings.supportRbPlus   = 1;
                 m_settings.dccUnsup3DSwDis = 0;
             }
+
+            if (ASICREV_IS_NAVY_FLOUNDER(chipRevision))
+            {
+                m_settings.supportRbPlus   = 1;
+                m_settings.dccUnsup3DSwDis = 0;
+            }
             break;
         default:
             ADDR_ASSERT(!"Unknown chip family");

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index f054edba1cebc7dfe45df4f0986497a348036fa3..a5fd949ac066f0685517b4378696b1a928c0b17d 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -410,6 +410,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                identify_chip(NAVI12);
                identify_chip(NAVI14);
                identify_chip(SIENNA_CICHLID);
+               identify_chip(NAVY_FLOUNDER);
                break;
        }
 
@@ -742,6 +743,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                case CHIP_NAVI10:
                case CHIP_NAVI12:
                case CHIP_SIENNA_CICHLID:
+               case CHIP_NAVY_FLOUNDER:
                        pc_lines = 1024;
                        break;
                case CHIP_NAVI14:

diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 7f581c4945a4d52dc08b6af3f9619ce9b7c7ebe6..485ae276306ad928c00c3254411185e7540338e5 100644 (file)
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -103,6 +103,7 @@ enum radeon_family {
     CHIP_NAVI12,
     CHIP_NAVI14,
     CHIP_SIENNA_CICHLID,
+    CHIP_NAVY_FLOUNDER,
     CHIP_LAST,
 };
 

diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c
index 8edef9c352277eaed54b81380e87ce6881c958d1..29f9352b886f9e0dbcf3614621c10c35e69431e7 100644 (file)
--- a/src/amd/llvm/ac_llvm_util.c
+++ b/src/amd/llvm/ac_llvm_util.c
@@ -157,6 +157,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
        case CHIP_NAVI14:
                return "gfx1012";
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                return "gfx1030";
        default:
                return "";

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 038546f56d45307d9999bdae2b8a0792a5c4b683..8ef797e68096f8304397252ac9813166e83d0ec7 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1590,6 +1590,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
       break;
    case CHIP_ARCTURUS:
    case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
       dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
       dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
       dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;