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radeonsi: reorder code in update_gs_ring_buffers and init_tess_factor_ring
author
Marek Olšák
<marek.olsak@amd.com>
Tue, 16 Jun 2020 17:57:24 +0000
(13:57 -0400)
committer
Marek Olšák
<marek.olsak@amd.com>
Wed, 22 Jul 2020 16:08:19 +0000
(12:08 -0400)
to reduce the churn when adding codepaths for shadowed registers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
src/gallium/drivers/radeonsi/si_state_shaders.c
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diff --git
a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 01ed224b282eb874c42599f5a078a29ea417cec0..3d3c688fbb1d1269d39781f6d55275aec54f2c4f 100644
(file)
--- a/
src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/
src/gallium/drivers/radeonsi/si_state_shaders.c
@@
-3377,6
+3377,19
@@
static bool si_update_gs_ring_buffers(struct si_context *sctx)
return false;
}
return false;
}
+ /* Set ring bindings. */
+ if (sctx->esgs_ring) {
+ assert(sctx->chip_class <= GFX8);
+ si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
+ true, 4, 64, 0);
+ si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
+ false, 0, 0, 0);
+ }
+ if (sctx->gsvs_ring) {
+ si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
+ false, 0, 0, 0);
+ }
+
/* Create the "cs_preamble_gs_rings" state. */
pm4 = CALLOC_STRUCT(si_pm4_state);
if (!pm4)
/* Create the "cs_preamble_gs_rings" state. */
pm4 = CALLOC_STRUCT(si_pm4_state);
if (!pm4)
@@
-3401,27
+3414,12
@@
static bool si_update_gs_ring_buffers(struct si_context *sctx)
si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
sctx->cs_preamble_gs_rings = pm4;
si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
sctx->cs_preamble_gs_rings = pm4;
- if (!sctx->cs_preamble_has_vgt_flush) {
- si_cs_preamble_add_vgt_flush(sctx);
- }
+ si_cs_preamble_add_vgt_flush(sctx);
/* Flush the context to re-emit both cs_preamble states. */
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
/* Flush the context to re-emit both cs_preamble states. */
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
- /* Set ring bindings. */
- if (sctx->esgs_ring) {
- assert(sctx->chip_class <= GFX8);
- si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
- true, 4, 64, 0);
- si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
- false, 0, 0, 0);
- }
- if (sctx->gsvs_ring) {
- si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
- false, 0, 0, 0);
- }
-
return true;
}
return true;
}
@@
-3637,11
+3635,11
@@
static void si_init_tess_factor_ring(struct si_context *sctx)
if (!sctx->tess_rings)
return;
if (!sctx->tess_rings)
return;
- si_cs_preamble_add_vgt_flush(sctx);
-
uint64_t factor_va =
si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size;
uint64_t factor_va =
si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size;
+ si_cs_preamble_add_vgt_flush(sctx);
+
/* Append these registers to the init config state. */
if (sctx->chip_class >= GFX7) {
si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE,
/* Append these registers to the init config state. */
if (sctx->chip_class >= GFX7) {
si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE,