radv/gfx9: only minify image view width/height/depth before gfx9.

For gfx9 the addressing for images has changed, so we need to
provide the hw with the level0, however we still need to scale
for format block differences (so our compressed upload paths still
work).

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a32f76d648ed5980a81af392db359fb9f8c698ff..1a7831e89c9c73ab27ba53c140804aca0402b6ae 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3130,8 +3130,8 @@ radv_initialise_color_surface(struct radv_device *device,
                cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
                cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
                        S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
-               cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
-                       S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
+               cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
+                       S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
                        S_028C68_MAX_MIP(iview->image->info.levels - 1);
 
                cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ddf15bc8361e265a26a0f0182303c892b0278d04..78f52a8f729b1c6911a5613da87f09248b77dc02 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -941,11 +941,19 @@ radv_image_view_init(struct radv_image_view *iview,
                iview->vk_format = vk_format_depth_only(iview->vk_format);
        }
 
-       iview->extent = (VkExtent3D) {
-               .width  = radv_minify(image->info.width , range->baseMipLevel),
-               .height = radv_minify(image->info.height, range->baseMipLevel),
-               .depth  = radv_minify(image->info.depth , range->baseMipLevel),
-       };
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
+               iview->extent = (VkExtent3D) {
+                       .width = image->info.width,
+                       .height = image->info.height,
+                       .depth = image->info.depth,
+               };
+       } else {
+               iview->extent = (VkExtent3D) {
+                       .width  = radv_minify(image->info.width , range->baseMipLevel),
+                       .height = radv_minify(image->info.height, range->baseMipLevel),
+                       .depth  = radv_minify(image->info.depth , range->baseMipLevel),
+               };
+       }
 
        if (iview->vk_format != image->vk_format) {
                iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),