gallium/radeon: add radeon_surf::is_linear

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 74bec2626030c13b2ec7dd5a68b83b0521f7f406..c6f4d0d86eceb7f860e4eff51d5bd45caae46e56 100644 (file)
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -160,7 +160,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
 
        /* Tiled textures are unmappable. Always put them in VRAM. */
        if (res->b.b.target != PIPE_BUFFER &&
-           rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
+           !rtex->surface.is_linear) {
                res->domains = RADEON_DOMAIN_VRAM;
                res->flags &= ~RADEON_FLAG_CPU_ACCESS;
                res->flags |= RADEON_FLAG_NO_CPU_ACCESS |

diff --git a/src/gallium/drivers/radeon/r600_test_dma.c b/src/gallium/drivers/radeon/r600_test_dma.c
index 7f4a8c0113d9a3f31f14d759ef18eb1080b174b1..f7e9eb5fc38495223f1cf0d45724d3cdba020b9b 100644 (file)
--- a/src/gallium/drivers/radeon/r600_test_dma.c
+++ b/src/gallium/drivers/radeon/r600_test_dma.c
@@ -331,8 +331,8 @@ void r600_test_dma(struct r600_common_screen *rscreen)
                                dstz = rand() % (tdst.array_size - depth + 1);
 
                                /* special code path to hit the tiled partial copies */
-                               if (rsrc->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
-                                   rdst->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
+                               if (!rsrc->surface.is_linear &&
+                                   !rdst->surface.is_linear &&
                                    rand() & 1) {
                                        if (max_width < 8 || max_height < 8)
                                                continue;
@@ -359,8 +359,8 @@ void r600_test_dma(struct r600_common_screen *rscreen)
                                }
 
                                /* special code path to hit out-of-bounds reads in L2T */
-                               if (rsrc->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
-                                   rdst->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
+                               if (rsrc->surface.is_linear &&
+                                   !rdst->surface.is_linear &&
                                    rand() % 4 == 0) {
                                        srcx = 0;
                                        srcy = 0;

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 065d0754a1a24ca199f3e6be2bdb3b3f3b23dbb0..ff45261014a200b621374eb7bfa7b6fd5d7659bf 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -425,7 +425,7 @@ static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
                return;
 
        if (rtex->resource.is_shared ||
-           rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
+           rtex->surface.is_linear)
                return;
 
        /* This fails with MSAA, depth, and compressed textures. */
@@ -1406,7 +1406,7 @@ static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
 
        /* There is no point in discarding depth and tiled buffers. */
        assert(!rtex->is_depth);
-       assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED);
+       assert(rtex->surface.is_linear);
 
        /* Reallocate the buffer in the same pipe_resource. */
        r600_alloc_resource(rscreen, &rtex->resource);
@@ -1465,7 +1465,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
                 * Use the staging texture for uploads if the underlying BO
                 * is busy.
                 */
-               if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
+               if (!rtex->surface.is_linear)
                        use_staging_texture = true;
                else if (usage & PIPE_TRANSFER_READ)
                        use_staging_texture = (rtex->resource.domains &
@@ -2446,7 +2446,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
                }
 
                /* only supported on tiled surfaces */
-               if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
+               if (tex->surface.is_linear) {
                        continue;
                }
 

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1e7035faa99c530512eb317bb177180e213c2a25..f65f6693ae33d38efa4216797a8799a42af9fd1f 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -294,6 +294,7 @@ struct radeon_surf {
      * the first level.
      */
     unsigned                    num_dcc_levels:4;
+    unsigned                    is_linear:1;
     uint32_t                    flags;
 
     /* These are return values. Some of them can be set by the caller, but

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index fe17f7392424de904e4f7ffee2e40e827267ddf5..0fd1106d59bae750360ca4bfe709f96fb37d65d0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1012,7 +1012,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
            info->src.box.width == dst_width &&
            info->src.box.height == dst_height &&
            info->src.box.depth == 1 &&
-           dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
+           !dst->surface.is_linear &&
            (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
                /* Check the last constraint. */
                if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
@@ -1116,8 +1116,7 @@ static void si_blit(struct pipe_context *ctx,
         * resource_copy_region can't do this yet, because dma_copy calls it
         * on failure (recursion).
         */
-       if (rdst->surface.level[info->dst.level].mode ==
-           RADEON_SURF_MODE_LINEAR_ALIGNED &&
+       if (rdst->surface.is_linear &&
            sctx->b.dma_copy &&
            util_can_blit_via_copy_region(info, false)) {
                sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index bf89d8bf1f2d03a2100ab25bec88129c472d3a5f..ab3397c5f190f7cba116d9fe809dca238a5ec305 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2360,7 +2360,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                        sctx->framebuffer.compressed_cb_mask |= 1 << i;
                }
 
-               if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
+               if (rtex->surface.is_linear)
                        sctx->framebuffer.any_dst_linear = true;
 
                r600_context_add_resource_size(ctx, surf->base.texture);

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index deae4dd3a1f6b8ea8dc4cc327a776c06d22649f2..d65dae726610df812721eca636a7bacf2087b3a5 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -566,6 +566,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    if (surf->htile_size && tex->last_level)
           surf->htile_size *= 2;
 
+   surf->is_linear = surf->level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
    return 0;
 }
 

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 95ec0eb8742f7dbdde3191dc051c17699f1ff90e..c6fa475fc4abf023e673ee463545fc316f37a84a 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -178,6 +178,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
     surf_ws->blk_w = surf_drm->blk_w;
     surf_ws->blk_h = surf_drm->blk_h;
     surf_ws->bpe = surf_drm->bpe;
+    surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
     surf_ws->flags = surf_drm->flags;
 
     surf_ws->surf_size = surf_drm->bo_size;