gallium/radeon: merge USER_SHADER and INTERNAL_SHADER priority flags

there's no reason to separate these

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index 292b5e32afd3675d8c5d7580d227ce65e14b9594..fe43f37574998ab42d0ff238ca954951d3ed17cf 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -584,7 +584,7 @@ void evergreen_emit_cs_shader(struct r600_context *rctx,
        radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
        radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
                                              code_bo, RADEON_USAGE_READ,
-                                             RADEON_PRIO_USER_SHADER));
+                                             RADEON_PRIO_SHADER_BINARY));
 }
 
 static void evergreen_launch_grid(struct pipe_context *ctx,

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 3d1a19d04f4d84ce7cbceed6d84652fb0b068da0..11c8161672ef0be8e1d900a63b74522edbb08b59 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2156,7 +2156,7 @@ static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
        radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
                                                   RADEON_USAGE_READ,
-                                                  RADEON_PRIO_INTERNAL_SHADER));
+                                                  RADEON_PRIO_SHADER_BINARY));
 }
 
 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 62b1c2c282a8c2242522183fa5e9a67a974a3eb8..fb2861a235958a4320bc42cb6c2467864de056ec 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1909,7 +1909,7 @@ static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
        radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
                                                   RADEON_USAGE_READ,
-                                                  RADEON_PRIO_INTERNAL_SHADER));
+                                                  RADEON_PRIO_SHADER_BINARY));
 }
 
 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 9008a4a71acffd17171a43d1c36d80c897ddf53d..a5341c3b420cf8af07200ba5cfb055e395d3d07e 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2156,7 +2156,7 @@ void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
        r600_emit_command_buffer(cs, &shader->command_buffer);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
        radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
-                                             RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER));
+                                             RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
 }
 
 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index c65b9a4a3d4c99086e92afe1a54aafdf870c5c8a..cbab406db88fc28c04acccf612e456d16718350a 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -186,8 +186,7 @@ enum radeon_bo_priority {
     RADEON_PRIO_SDMA_TEXTURE,
 
     RADEON_PRIO_CP_DMA = 12,
-    RADEON_PRIO_USER_SHADER,
-    RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
+    RADEON_PRIO_SHADER_BINARY,
 
     RADEON_PRIO_CONST_BUFFER = 16,
     RADEON_PRIO_DESCRIPTORS,

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index c3e8a35ba1d9aa60f8e9b9c2e836685cbf63952a..17a4125122b4409fb5b0ed206eeef9cfc8ea1cdf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -288,7 +288,7 @@ static bool si_switch_compute_shader(struct si_context *sctx,
        shader_va = shader->bo->gpu_address + offset;
 
        radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
-                                 RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+                                 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
        radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
        radeon_emit(cs, shader_va >> 8);

diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index a52dfe4e732578b5baf53008a68827b1a5c82dd6..4b500cfffa0e315b2bcde614333486c33679dc2d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -553,8 +553,7 @@ static const char *priority_to_string(enum radeon_bo_priority priority)
                ITEM(SDMA_BUFFER),
                ITEM(SDMA_TEXTURE),
                ITEM(CP_DMA),
-               ITEM(USER_SHADER),
-               ITEM(INTERNAL_SHADER),
+               ITEM(SHADER_BINARY),
                ITEM(CONST_BUFFER),
                ITEM(DESCRIPTORS),
                ITEM(BORDER_COLORS),

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index d82139745b9f2f5c6fc7c02aa859275b76d1398d..394afaa972598f017e7aa25ddcc6af405009fa86 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -340,7 +340,7 @@ static void si_shader_ls(struct si_shader *shader)
                return;
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
        /* We need at least 2 components for LS.
         * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
@@ -368,7 +368,7 @@ static void si_shader_hs(struct si_shader *shader)
                return;
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
        si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
        si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
@@ -397,7 +397,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
                return;
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
        if (shader->selector->type == PIPE_SHADER_VERTEX) {
                vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
@@ -492,7 +492,7 @@ static void si_shader_gs(struct si_shader *shader)
                       S_028B90_ENABLE(gs_num_invocations > 0));
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
        si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
        si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
 
@@ -547,7 +547,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
        }
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
        if (gs) {
                vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
@@ -757,7 +757,7 @@ static void si_shader_ps(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
 
        va = shader->bo->gpu_address;
-       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+       si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
        si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
        si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);