intel/nir: Allow splitting a single load into up to 32 loads
authorJason Ekstrand <jason@jlekstrand.net>
Fri, 21 Aug 2020 04:59:54 +0000 (23:59 -0500)
committerMarge Bot <eric+marge@anholt.net>
Fri, 21 Aug 2020 22:49:54 +0000 (22:49 +0000)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>

src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c

index f67a414e873083309a223931ceb8897836615a2a..c26ea0bb7783c3633d22cdd1b322dc64e26ab9ce 100644 (file)
@@ -109,8 +109,10 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
       result = nir_extract_bits(b, &load, 1, load_offset * 8,
                                 num_components, bit_size);
    } else {
       result = nir_extract_bits(b, &load, 1, load_offset * 8,
                                 num_components, bit_size);
    } else {
-      /* Otherwise, we have to break it into smaller loads */
-      nir_ssa_def *loads[8];
+      /* Otherwise, we have to break it into smaller loads.  We could end up
+       * with as many as 32 loads if we're loading a u64vec16 from scratch.
+       */
+      nir_ssa_def *loads[32];
       unsigned num_loads = 0;
       int load_offset = 0;
       while (load_offset < bytes_read) {
       unsigned num_loads = 0;
       int load_offset = 0;
       while (load_offset < bytes_read) {