radv: Emit cache flushes before CP DMA.

The flushes could be due to TRANSFER barriers.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 5d35287f8e37e59cd84d4a02165bfd79b26f07f3..b808052ddb24a8daf84d93a7b3f0a728be1c5f7a 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -998,6 +998,7 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
        uint64_t main_src_va, main_dest_va;
        uint64_t skipped_size = 0, realign_size = 0;
 
+       si_emit_cache_flush(cmd_buffer);
 
        if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
            cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
@@ -1061,6 +1062,8 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 
        assert(va % 4 == 0 && size % 4 == 0);
 
+       si_emit_cache_flush(cmd_buffer);
+
        while (size) {
                unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
                unsigned dma_flags = 0;