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amd/common: unify PITCH_GFX6 and PITCH_GFX9
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Mon, 6 May 2019 23:44:52 +0000 (01:44 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 4 Jun 2019 00:05:20 +0000 (20:05 -0400)
The definition of the fields differs, but PITCH_GFX9 is a mere extension
of PITCH_GFX6 that does not conflict with any other fields.

This aligns the definitions with what will be generated from the
register JSON.

The information about how large the fields really are is preserved in
the register database.

src/amd/common/gfx9d.h patch | blob | history
src/amd/common/sid.h patch | blob | history
src/amd/vulkan/radv_image.c patch | blob | history
src/gallium/drivers/radeonsi/si_descriptors.c patch | blob | history
src/gallium/drivers/radeonsi/si_state.c patch | blob | history

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index 5d3de5842a17bdbd679b6723e54d2d57a191866d..4aa6821ad64b062cff7859b4d76188212a12db5e 100644 (file)
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1446,9 +1446,9 @@
 #define   S_008F20_DEPTH(x)                                           (((unsigned)(x) & 0x1FFF) << 0)
 #define   G_008F20_DEPTH(x)                                           (((x) >> 0) & 0x1FFF)
 #define   C_008F20_DEPTH                                              0xFFFFE000
-#define   S_008F20_PITCH_GFX9(x)                                      (((unsigned)(x) & 0xFFFF) << 13)
-#define   G_008F20_PITCH_GFX9(x)                                      (((x) >> 13) & 0xFFFF)
-#define   C_008F20_PITCH_GFX9                                         0xE0001FFF
+#define   S_008F20_PITCH(x)                                           (((unsigned)(x) & 0xFFFF) << 13)
+#define   G_008F20_PITCH(x)                                           (((x) >> 13) & 0xFFFF)
+#define   C_008F20_PITCH                                              0xE0001FFF
 #define   S_008F20_BC_SWIZZLE(x)                                      (((unsigned)(x) & 0x07) << 29)
 #define   G_008F20_BC_SWIZZLE(x)                                      (((x) >> 29) & 0x07)
 #define   C_008F20_BC_SWIZZLE                                         0x1FFFFFFF
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 1e6d2595c3c5f9c2c90da00d64c3d36eca3780ac..930e70e8ebd53d9e74b8c056b7ee71e20211301e 100644 (file)
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -2326,9 +2326,9 @@
 #define   S_008F20_DEPTH(x)                                           (((unsigned)(x) & 0x1FFF) << 0)
 #define   G_008F20_DEPTH(x)                                           (((x) >> 0) & 0x1FFF)
 #define   C_008F20_DEPTH                                              0xFFFFE000
-#define   S_008F20_PITCH_GFX6(x)                                      (((unsigned)(x) & 0x3FFF) << 13)
-#define   G_008F20_PITCH_GFX6(x)                                      (((x) >> 13) & 0x3FFF)
-#define   C_008F20_PITCH_GFX6                                         0xF8001FFF
+#define   S_008F20_PITCH(x)                                           (((unsigned)(x) & 0xFFFF) << 13)
+#define   G_008F20_PITCH(x)                                           (((x) >> 13) & 0xFFFF)
+#define   C_008F20_PITCH                                              0xE0001FFF
 #define R_008F24_SQ_IMG_RSRC_WORD5                                      0x008F24
 #define   S_008F24_BASE_ARRAY(x)                                      (((unsigned)(x) & 0x1FFF) << 0)
 #define   G_008F24_BASE_ARRAY(x)                                      (((x) >> 0) & 0x1FFF)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index fbfabea3b6f52febd01bdcc243a46dc1bf638570..4f06d4f97f50ab0728f676a8c06be464b6b5a59e 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -398,14 +398,14 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
        if (chip_class >= GFX9) {
                state[3] &= C_008F1C_SW_MODE;
-               state[4] &= C_008F20_PITCH_GFX9;
+               state[4] &= C_008F20_PITCH;
 
                if (is_stencil) {
                        state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
-                       state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
+                       state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
                } else {
                        state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
-                       state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
+                       state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
                }
 
                state[5] &= C_008F24_META_DATA_ADDRESS &
@@ -430,8 +430,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
                state[3] &= C_008F1C_TILING_INDEX;
                state[3] |= S_008F1C_TILING_INDEX(index);
-               state[4] &= C_008F20_PITCH_GFX6;
-               state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
+               state[4] &= C_008F20_PITCH;
+               state[4] |= S_008F20_PITCH(pitch - 1);
        }
 }
 
@@ -674,13 +674,13 @@ si_make_texture_descriptor(struct radv_device *device,
                if (device->physical_device->rad_info.chip_class >= GFX9) {
                        fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
                        fmask_state[4] |= S_008F20_DEPTH(last_layer) |
-                                         S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
+                                         S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
                        fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
                                          S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
                } else {
                        fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
                        fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
-                               S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
+                               S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
                        fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
                }
        } else if (fmask_state)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 1cb0ac93caae5319ce37779f6af8b67530c86560..241c98f6343ab4f6429cc32ccb8663df5495fa31 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -366,14 +366,14 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
        if (sscreen->info.chip_class >= GFX9) {
                state[3] &= C_008F1C_SW_MODE;
-               state[4] &= C_008F20_PITCH_GFX9;
+               state[4] &= C_008F20_PITCH;
 
                if (is_stencil) {
                        state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
-                       state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
+                       state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch);
                } else {
                        state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
-                       state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch);
+                       state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch);
                }
 
                state[5] &= C_008F24_META_DATA_ADDRESS &
@@ -398,8 +398,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
                state[3] &= C_008F1C_TILING_INDEX;
                state[3] |= S_008F1C_TILING_INDEX(index);
-               state[4] &= C_008F20_PITCH_GFX6;
-               state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
+               state[4] &= C_008F20_PITCH;
+               state[4] |= S_008F20_PITCH(pitch - 1);
        }
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e86ff29f0a59a90a28100c3e32e765bda0b34c77..5ca972494b3ab28363b0049ca36b928a0fe531a2 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4023,13 +4023,13 @@ si_make_texture_descriptor(struct si_screen *screen,
                if (screen->info.chip_class >= GFX9) {
                        fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
                        fmask_state[4] |= S_008F20_DEPTH(last_layer) |
-                                         S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
+                                         S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
                        fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
                                          S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
                } else {
                        fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
                        fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
-                                         S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
+                                         S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
                        fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
                }
        }