freedreno/ir3: add ir3_finalize_nir()

The next step is to hook this into pscreen->finalize_nir() so it can
come before the state tracker's shader-caching.

Unfortunately we still need to do lower_io after mesa/st, so that is
split out into a post-finalize pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index bf2db6b6c9cb470a593dc0308b4e23234c604fa4..5c15f5b8dfca616370d2288543c99da8ff68feab 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -215,14 +215,14 @@ should_split_wrmask(const nir_instr *instr, const void *data)
 }
 
 void
-ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
+ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
 {
        struct nir_lower_tex_options tex_options = {
                        .lower_rect = 0,
                        .lower_tg4_offsets = true,
        };
 
-       if (shader->compiler->gpu_id >= 400) {
+       if (compiler->gpu_id >= 400) {
                /* a4xx seems to have *no* sam.p */
                tex_options.lower_txp = ~0;  /* lower all txp */
        } else {
@@ -236,17 +236,19 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
                debug_printf("----------------------\n");
        }
 
-       OPT_V(s, nir_lower_regs_to_ssa);
-       OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
+       if (s->info.stage == MESA_SHADER_GEOMETRY)
+               NIR_PASS_V(s, ir3_nir_lower_gs);
 
-       OPT_V(s, ir3_nir_apply_trig_workarounds);
+       NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
 
-       if (shader->type == MESA_SHADER_FRAGMENT)
-               OPT_V(s, nir_lower_fb_read);
+       NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
+
+       OPT_V(s, nir_lower_regs_to_ssa);
+       OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
 
        OPT_V(s, nir_lower_tex, &tex_options);
        OPT_V(s, nir_lower_load_const_to_scalar);
-       if (shader->compiler->gpu_id < 500)
+       if (compiler->gpu_id < 500)
                OPT_V(s, ir3_nir_lower_tg4_to_tex);
 
        ir3_optimize_loop(s);
@@ -270,6 +272,39 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
        nir_sweep(s);
 }
 
+/**
+ * Late passes that need to be done after pscreen->finalize_nir()
+ */
+void
+ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
+{
+       NIR_PASS_V(s, nir_lower_io, nir_var_all, ir3_glsl_type_size,
+                          (nir_lower_io_options)0);
+
+       if (s->info.stage == MESA_SHADER_FRAGMENT) {
+               /* NOTE: lower load_barycentric_at_sample first, since it
+                * produces load_barycentric_at_offset:
+                */
+               NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
+               NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
+               NIR_PASS_V(s, ir3_nir_move_varying_inputs);
+               NIR_PASS_V(s, nir_lower_fb_read);
+       }
+
+       if (compiler->gpu_id >= 600 &&
+                       s->info.stage == MESA_SHADER_FRAGMENT &&
+                       !(ir3_shader_debug & IR3_DBG_NOFP16)) {
+               NIR_PASS_V(s, nir_lower_mediump_outputs);
+       }
+
+       /* we cannot ensure that ir3_finalize_nir() is only called once, so
+        * we also need to do trig workarounds here:
+        */
+       OPT_V(s, ir3_nir_apply_trig_workarounds);
+
+       ir3_optimize_loop(s);
+}
+
 void
 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 {

diff --git a/src/freedreno/ir3/ir3_nir.h b/src/freedreno/ir3/ir3_nir.h
index b84525bd69f267972beaae0c0326c714549c0664..8bc6d342fe0b16875a5f7c2e8e37197da7c81f71 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.h
+++ b/src/freedreno/ir3/ir3_nir.h
@@ -52,7 +52,8 @@ void ir3_nir_lower_tess_eval(nir_shader *shader, unsigned topology);
 void ir3_nir_lower_gs(nir_shader *shader);
 
 const nir_shader_compiler_options * ir3_get_compiler_options(struct ir3_compiler *compiler);
-void ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s);
+void ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s);
+void ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s);
 void ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s);
 
 void ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,

diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index 37e1f8bfb2cc00d309c3bc861e40ced5cfc3b912..afdce9d0f828d5401e0bd3ee2fa878cae29f5e9e 100644 (file)
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -409,35 +409,12 @@ ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
                memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
        shader->num_reserved_user_consts = reserved_user_consts;
 
-       if (nir->info.stage == MESA_SHADER_GEOMETRY)
-               NIR_PASS_V(nir, ir3_nir_lower_gs);
+       ir3_nir_post_finalize(compiler, nir);
 
-       NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
-                          (nir_lower_io_options)0);
-
-       if (compiler->gpu_id >= 600 &&
-                       nir->info.stage == MESA_SHADER_FRAGMENT &&
-                       !(ir3_shader_debug & IR3_DBG_NOFP16))
-               NIR_PASS_V(nir, nir_lower_mediump_outputs);
-
-       if (nir->info.stage == MESA_SHADER_FRAGMENT) {
-               /* NOTE: lower load_barycentric_at_sample first, since it
-                * produces load_barycentric_at_offset:
-                */
-               NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
-               NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
-
-               NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
-       }
-
-       NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
-
-       NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
-
-       /* do first pass optimization, ignoring the key: */
-       ir3_optimize_nir(shader, nir);
+       ir3_finalize_nir(compiler, nir);
 
        shader->nir = nir;
+
        if (ir3_shader_debug & IR3_DBG_DISASM) {
                printf("dump nir%d: type=%d", shader->id, shader->type);
                nir_print_shader(shader->nir, stdout);

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index cd9950436c5cfcb3fb6eecbc66ae85078754bc27..0498c5828ad31ebeec1c2c3dc6b06f42eeec1648 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -491,7 +491,7 @@ int main(int argc, char **argv)
        s.compiler = compiler;
        s.nir = nir;
 
-       ir3_optimize_nir(&s, nir);
+       ir3_finalize_nir(compiler, nir);
 
        v.key = key;
        v.shader = &s;