intel/blorp: Fill out all the dwords of MI_ATOMIC

This makes us valgrind clean again.

Fixes: 9175c7058efb "intel/blorp: Make blorp update the clear color..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3366>

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 348970a491bcb6ce1c94c4cbec74b165fe7e5dc5..9db829c30f21775ee4a9c1e254cf2a8138816b0a 100644 (file)
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1792,7 +1792,9 @@ blorp_update_clear_color(struct blorp_batch *batch,
                                  .MemoryAddress = clear_addr);
       /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
       dw[2] = info->clear_color.u32[0];
+      dw[3] = 0;
       dw[4] = info->clear_color.u32[1];
+      dw[5] = 0;
 
       clear_addr.offset += 8;
       dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords,
@@ -1804,7 +1806,9 @@ blorp_update_clear_color(struct blorp_batch *batch,
                                  .MemoryAddress = clear_addr);
       /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
       dw[2] = info->clear_color.u32[2];
+      dw[3] = 0;
       dw[4] = info->clear_color.u32[3];
+      dw[5] = 0;
 
       blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
          pipe.StateCacheInvalidationEnable = true;