freedreno: a2xx: implement texture tiling
authorJonathan Marek <jonathan@marek.ca>
Thu, 1 Aug 2019 18:41:44 +0000 (14:41 -0400)
committerJonathan Marek <jonathan@marek.ca>
Fri, 2 Aug 2019 15:58:22 +0000 (15:58 +0000)
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
src/freedreno/registers/a2xx.xml
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
src/gallium/drivers/freedreno/a2xx/fd2_resource.c
src/gallium/drivers/freedreno/a2xx/fd2_resource.h
src/gallium/drivers/freedreno/a2xx/fd2_screen.c
src/gallium/drivers/freedreno/a2xx/fd2_texture.c
src/gallium/drivers/freedreno/freedreno_screen.c

index ff98e4d17dddbc6dfd84226bceec4a7215f24e9f..1b0bf44bd3d5f11a9b836bf01af6d8163b83e8ae 100644 (file)
@@ -1596,7 +1596,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
                <bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>"
                <bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>"
                <bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
-               <bitfield name="TILED" pos="1" type="boolean"/>
+               <bitfield name="TILED" pos="31" type="boolean"/>
        </reg32>
        <reg32 offset="1" name="1">
                <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
index 47cbb54d611882ecacfd101f9becf9765992297c..20c6b8bbdca678e40afc55e22d2f82562467971e 100644 (file)
@@ -114,7 +114,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
        OUT_RING(ring, slice->pitch >> 5); /* RB_COPY_DEST_PITCH */
        OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
                        A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
-                       A2XX_RB_COPY_DEST_INFO_LINEAR |
+                       COND(!rsc->tile_mode, A2XX_RB_COPY_DEST_INFO_LINEAR) |
                        A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
                        A2XX_RB_COPY_DEST_INFO_WRITE_RED |
                        A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
@@ -456,7 +456,8 @@ fd2_emit_sysmem_prep(struct fd_batch *batch)
 
        OUT_PKT3(ring, CP_SET_CONSTANT, 2);
        OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
-       OUT_RELOCW(ring, rsc->bo, offset, A2XX_RB_COLOR_INFO_LINEAR |
+       OUT_RELOCW(ring, rsc->bo, offset,
+               COND(!rsc->tile_mode, A2XX_RB_COLOR_INFO_LINEAR) |
                A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
                A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)), 0);
 
index 2c813804689b0535061605dd902e52af633c0b0a..27e9500ff883ca2e06b5dc7901cfcac36c3548b6 100644 (file)
@@ -77,3 +77,15 @@ fd2_setup_slices(struct fd_resource *rsc)
        }
        return size;
 }
+
+unsigned
+fd2_tile_mode(const struct pipe_resource *tmpl)
+{
+       /* disable tiling for cube maps, freedreno uses a 2D array for the staging texture,
+       * (a2xx supports 2D arrays but it is not implemented)
+       */
+       if (tmpl->target == PIPE_TEXTURE_CUBE)
+               return 0;
+       /* we can enable tiling for any resource we can render to */
+       return (tmpl->bind & PIPE_BIND_RENDER_TARGET) ? 1 : 0;
+}
index 7a9d356bf447e53a008296e7d82a205b4968c15c..eb1221a096cebd80f16f17b1e55f6705fd645ea0 100644 (file)
@@ -30,5 +30,6 @@
 #include "freedreno_resource.h"
 
 uint32_t fd2_setup_slices(struct fd_resource *rsc);
+unsigned fd2_tile_mode(const struct pipe_resource *tmpl);
 
 #endif /* FD2_RESOURCE_H_ */
index 2e97e9d6e445a0bfaf1f413d0b10691ef153ccf7..0c02c6a7e05a4234d22a78eb71a7c575668a7bf6 100644 (file)
@@ -116,7 +116,10 @@ fd2_screen_init(struct pipe_screen *pscreen)
        screen->max_rts = 1;
        pscreen->context_create = fd2_context_create;
        pscreen->is_format_supported = fd2_screen_is_format_supported;
+
        screen->setup_slices = fd2_setup_slices;
+       if (fd_mesa_debug & FD_DBG_TTILE)
+               screen->tile_mode = fd2_tile_mode;
 
        if (fd_mesa_debug & FD_DBG_PERFC) {
                screen->perfcntr_groups = a2xx_perfcntr_groups;
index 3e3add798bc0060852c0c6cd0d13e6ed9f04cbc4..3aca767f2859ee8134b58e70eb9ff17d050cda66 100644 (file)
@@ -180,7 +180,9 @@ fd2_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
        so->base.reference.count = 1;
        so->base.context = pctx;
 
-       so->tex0 = A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch);
+       so->tex0 =
+               A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch) |
+               COND(rsc->tile_mode, A2XX_SQ_TEX_0_TILED);
        so->tex1 =
                A2XX_SQ_TEX_1_FORMAT(fd2_pipe2surface(cso->format)) |
                A2XX_SQ_TEX_1_CLAMP_POLICY(SQ_TEX_CLAMP_POLICY_OGL);
index 2de02e31fe31d5c2a3e074ae1e759fc87a3ca26e..e9cd34aa3844efae9d52cbd8adee059e7fb1212c 100644 (file)
@@ -85,7 +85,7 @@ static const struct debug_named_value debug_options[] = {
                {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
                {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
                {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
-               {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
+               {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a5xx)"},
                {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
                {"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
                DEBUG_NAMED_VALUE_END