freedreno: Generate headers from xml files
authorKristian H. Kristensen <hoegsberg@google.com>
Tue, 11 Jun 2019 18:27:36 +0000 (11:27 -0700)
committerKristian H. Kristensen <hoegsberg@gmail.com>
Wed, 10 Jul 2019 22:05:02 +0000 (22:05 +0000)
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Rob Clark <robdclark@gmail.com>
29 files changed:
src/freedreno/Android.mk
src/freedreno/Android.registers.mk [new file with mode: 0644]
src/freedreno/Makefile.sources
src/freedreno/meson.build
src/freedreno/registers/a2xx.xml [new file with mode: 0644]
src/freedreno/registers/a2xx.xml.h [deleted file]
src/freedreno/registers/a3xx.xml [new file with mode: 0644]
src/freedreno/registers/a3xx.xml.h [deleted file]
src/freedreno/registers/a4xx.xml [new file with mode: 0644]
src/freedreno/registers/a4xx.xml.h [deleted file]
src/freedreno/registers/a5xx.xml [new file with mode: 0644]
src/freedreno/registers/a5xx.xml.h [deleted file]
src/freedreno/registers/a6xx.xml [new file with mode: 0644]
src/freedreno/registers/a6xx.xml.h [deleted file]
src/freedreno/registers/adreno_common.xml [new file with mode: 0644]
src/freedreno/registers/adreno_common.xml.h [deleted file]
src/freedreno/registers/adreno_pm4.xml [new file with mode: 0644]
src/freedreno/registers/adreno_pm4.xml.h [deleted file]
src/freedreno/registers/freedreno_copyright.xml [new file with mode: 0644]
src/freedreno/registers/gen_header.py [new file with mode: 0644]
src/freedreno/registers/meson.build [new file with mode: 0644]
src/freedreno/vulkan/meson.build
src/freedreno/vulkan/tu_cmd_buffer.c
src/freedreno/vulkan/tu_meta_copy.c
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
src/gallium/drivers/freedreno/a6xx/fd6_compute.c
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
src/gallium/drivers/freedreno/meson.build

index e46e2199dc1e3b1aaf65435a08e6d58be393a674..84d0c82c2cbb081b96e5b51a0a424edc5179ec16 100644 (file)
@@ -28,3 +28,4 @@ include $(LOCAL_PATH)/Makefile.sources
 include $(MESA_TOP)/src/gallium/drivers/freedreno/Android.gen.mk
 include $(LOCAL_PATH)/Android.drm.mk
 include $(LOCAL_PATH)/Android.ir3.mk
+include $(LOCAL_PATH)/Android.registers.mk
diff --git a/src/freedreno/Android.registers.mk b/src/freedreno/Android.registers.mk
new file mode 100644 (file)
index 0000000..e39e330
--- /dev/null
@@ -0,0 +1,58 @@
+# Mesa 3-D graphics library
+#
+# Copyright (C)
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+# Android.mk for libfreedreno_registers.a
+
+# ---------------------------------------
+# Build libfreedreno_registers
+# ---------------------------------------
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libfreedreno_registers
+
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+
+intermediates := $(call local-generated-sources-dir)
+
+# dummy.c source file is generated to meet the build system's rules.
+LOCAL_GENERATED_SOURCES += $(intermediates)/dummy.c
+
+$(intermediates)/dummy.c:
+       @mkdir -p $(dir $@)
+       @echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))"
+       $(hide) touch $@
+
+# This is the list of auto-generated files headers
+LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/registers/, \
+       a2xx.xml.h a3xx.xml.h a4xx.xml.h a5xx.xml.h a6xx.xml.h adreno_common.xml.h adreno_pm4.xml.h)
+
+$(intermediates)/registers/%.xml.h: $(LOCAL_PATH)/registers/%.xml $(LOCAL_PATH)/registers/gen_header.py
+       @mkdir -p $(dir $@)
+       @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
+       $(hide) $(MESA_PYTHON2) $(LOCAL_PATH)/registers/gen_header.py $< > $@
+
+LOCAL_EXPORT_C_INCLUDE_DIRS := \
+       $(intermediates)
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
index d8aaf2caeccfb1f009688a51bbfb31ce1bdb6720..5b983266a628f8886a22e39985edd6c29a5c2d5c 100644 (file)
@@ -49,12 +49,3 @@ ir3_SOURCES := \
 
 ir3_GENERATED_FILES := \
        ir3/ir3_nir_trig.c
-
-registers_FILES := \
-       registers/a2xx.xml.h \
-       registers/a3xx.xml.h \
-       registers/a4xx.xml.h \
-       registers/a5xx.xml.h \
-       registers/a6xx.xml.h \
-       registers/adreno_common.xml.h \
-       registers/adreno_pm4.xml.h
index 3f77b1d933e67e4bd5a8c4c775c07ac6a93e38fe..028ca9f106657070fe033dbaede49cee8eaecd70 100644 (file)
@@ -22,6 +22,7 @@ inc_freedreno = include_directories(['.', './registers'])
 
 subdir('drm')
 subdir('ir3')
+subdir('registers')
 
 if with_freedreno_vk
   subdir('vulkan')
diff --git a/src/freedreno/registers/a2xx.xml b/src/freedreno/registers/a2xx.xml
new file mode 100644 (file)
index 0000000..ff98e4d
--- /dev/null
@@ -0,0 +1,1650 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+
+<enum name="a2xx_rb_dither_type">
+       <value name="DITHER_PIXEL" value="0"/>
+       <value name="DITHER_SUBPIXEL" value="1"/>
+</enum>
+
+<enum name="a2xx_colorformatx">
+       <value name="COLORX_4_4_4_4" value="0"/>
+       <value name="COLORX_1_5_5_5" value="1"/>
+       <value name="COLORX_5_6_5" value="2"/>
+       <value name="COLORX_8" value="3"/>
+       <value name="COLORX_8_8" value="4"/>
+       <value name="COLORX_8_8_8_8" value="5"/>
+       <value name="COLORX_S8_8_8_8" value="6"/>
+       <value name="COLORX_16_FLOAT" value="7"/>
+       <value name="COLORX_16_16_FLOAT" value="8"/>
+       <value name="COLORX_16_16_16_16_FLOAT" value="9"/>
+       <value name="COLORX_32_FLOAT" value="10"/>
+       <value name="COLORX_32_32_FLOAT" value="11"/>
+       <value name="COLORX_32_32_32_32_FLOAT" value="12"/>
+       <value name="COLORX_2_3_3" value="13"/>
+       <value name="COLORX_8_8_8" value="14"/>
+</enum>
+
+<enum name="a2xx_sq_surfaceformat">
+       <value name="FMT_1_REVERSE" value="0"/>
+       <value name="FMT_1" value="1"/>
+       <value name="FMT_8" value="2"/>
+       <value name="FMT_1_5_5_5" value="3"/>
+       <value name="FMT_5_6_5" value="4"/>
+       <value name="FMT_6_5_5" value="5"/>
+       <value name="FMT_8_8_8_8" value="6"/>
+       <value name="FMT_2_10_10_10" value="7"/>
+       <value name="FMT_8_A" value="8"/>
+       <value name="FMT_8_B" value="9"/>
+       <value name="FMT_8_8" value="10"/>
+       <value name="FMT_Cr_Y1_Cb_Y0" value="11"/>
+       <value name="FMT_Y1_Cr_Y0_Cb" value="12"/>
+       <value name="FMT_5_5_5_1" value="13"/>
+       <value name="FMT_8_8_8_8_A" value="14"/>
+       <value name="FMT_4_4_4_4" value="15"/>
+       <value name="FMT_8_8_8" value="16"/>
+       <value name="FMT_DXT1" value="18"/>
+       <value name="FMT_DXT2_3" value="19"/>
+       <value name="FMT_DXT4_5" value="20"/>
+       <value name="FMT_10_10_10_2" value="21"/>
+       <value name="FMT_24_8" value="22"/>
+       <value name="FMT_16" value="24"/>
+       <value name="FMT_16_16" value="25"/>
+       <value name="FMT_16_16_16_16" value="26"/>
+       <value name="FMT_16_EXPAND" value="27"/>
+       <value name="FMT_16_16_EXPAND" value="28"/>
+       <value name="FMT_16_16_16_16_EXPAND" value="29"/>
+       <value name="FMT_16_FLOAT" value="30"/>
+       <value name="FMT_16_16_FLOAT" value="31"/>
+       <value name="FMT_16_16_16_16_FLOAT" value="32"/>
+       <value name="FMT_32" value="33"/>
+       <value name="FMT_32_32" value="34"/>
+       <value name="FMT_32_32_32_32" value="35"/>
+       <value name="FMT_32_FLOAT" value="36"/>
+       <value name="FMT_32_32_FLOAT" value="37"/>
+       <value name="FMT_32_32_32_32_FLOAT" value="38"/>
+       <value name="FMT_ATI_TC_RGB" value="39"/>
+       <value name="FMT_ATI_TC_RGBA" value="40"/>
+       <value name="FMT_ATI_TC_555_565_RGB" value="41"/>
+       <value name="FMT_ATI_TC_555_565_RGBA" value="42"/>
+       <value name="FMT_ATI_TC_RGBA_INTERP" value="43"/>
+       <value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/>
+       <value name="FMT_ETC1_RGBA_INTERP" value="46"/>
+       <value name="FMT_ETC1_RGB" value="47"/>
+       <value name="FMT_ETC1_RGBA" value="48"/>
+       <value name="FMT_DXN" value="49"/>
+       <value name="FMT_2_3_3" value="51"/>
+       <value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/>
+       <value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/>
+       <value name="FMT_32_32_32_FLOAT" value="57"/>
+       <value name="FMT_DXT3A" value="58"/>
+       <value name="FMT_DXT5A" value="59"/>
+       <value name="FMT_CTX1" value="60"/>
+</enum>
+
+<enum name="a2xx_sq_ps_vtx_mode">
+       <value name="POSITION_1_VECTOR" value="0"/>
+       <value name="POSITION_2_VECTORS_UNUSED" value="1"/>
+       <value name="POSITION_2_VECTORS_SPRITE" value="2"/>
+       <value name="POSITION_2_VECTORS_EDGE" value="3"/>
+       <value name="POSITION_2_VECTORS_KILL" value="4"/>
+       <value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/>
+       <value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/>
+       <value name="MULTIPASS" value="7"/>
+</enum>
+
+<enum name="a2xx_sq_sample_cntl">
+       <value name="CENTROIDS_ONLY" value="0"/>
+       <value name="CENTERS_ONLY" value="1"/>
+       <value name="CENTROIDS_AND_CENTERS" value="2"/>
+</enum>
+
+<enum name="a2xx_dx_clip_space">
+       <value name="DXCLIP_OPENGL" value="0"/>
+       <value name="DXCLIP_DIRECTX" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_su_sc_polymode">
+       <value name="POLY_DISABLED" value="0"/>
+       <value name="POLY_DUALMODE" value="1"/>
+</enum>
+
+<enum name="a2xx_rb_edram_mode">
+       <value name="EDRAM_NOP" value="0"/>
+       <value name="COLOR_DEPTH" value="4"/>
+       <value name="DEPTH_ONLY" value="5"/>
+       <value name="EDRAM_COPY" value="6"/>
+</enum>
+
+<enum name="a2xx_pa_sc_pattern_bit_order">
+       <value name="LITTLE" value="0"/>
+       <value name="BIG" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_sc_auto_reset_cntl">
+       <value name="NEVER" value="0"/>
+       <value name="EACH_PRIMITIVE" value="1"/>
+       <value name="EACH_PACKET" value="2"/>
+</enum>
+
+<enum name="a2xx_pa_pixcenter">
+       <value name="PIXCENTER_D3D" value="0"/>
+       <value name="PIXCENTER_OGL" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_roundmode">
+       <value name="TRUNCATE" value="0"/>
+       <value name="ROUND" value="1"/>
+       <value name="ROUNDTOEVEN" value="2"/>
+       <value name="ROUNDTOODD" value="3"/>
+</enum>
+
+<enum name="a2xx_pa_quantmode">
+       <value name="ONE_SIXTEENTH" value="0"/>
+       <value name="ONE_EIGTH" value="1"/>
+       <value name="ONE_QUARTER" value="2"/>
+       <value name="ONE_HALF" value="3"/>
+       <value name="ONE" value="4"/>
+</enum>
+
+<enum name="a2xx_rb_copy_sample_select">
+       <value name="SAMPLE_0" value="0"/>
+       <value name="SAMPLE_1" value="1"/>
+       <value name="SAMPLE_2" value="2"/>
+       <value name="SAMPLE_3" value="3"/>
+       <value name="SAMPLE_01" value="4"/>
+       <value name="SAMPLE_23" value="5"/>
+       <value name="SAMPLE_0123" value="6"/>
+</enum>
+
+<enum name="a2xx_rb_blend_opcode">
+       <value name="BLEND2_DST_PLUS_SRC" value="0"/>
+       <value name="BLEND2_SRC_MINUS_DST" value="1"/>
+       <value name="BLEND2_MIN_DST_SRC" value="2"/>
+       <value name="BLEND2_MAX_DST_SRC" value="3"/>
+       <value name="BLEND2_DST_MINUS_SRC" value="4"/>
+       <value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/>
+</enum>
+
+<enum name="a2xx_su_perfcnt_select">
+       <value value="0" name="PERF_PAPC_PASX_REQ"/>
+       <value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/>
+       <value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/>
+       <value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/>
+       <value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/>
+       <value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/>
+       <value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/>
+       <value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/>
+       <value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/>
+       <value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/>
+       <value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/>
+       <value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/>
+       <value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/>
+       <value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/>
+       <value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/>
+       <value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/>
+       <value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/>
+       <value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/>
+       <value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/>
+       <value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/>
+       <value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/>
+       <value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/>
+       <value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/>
+       <value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/>
+       <value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/>
+       <value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/>
+       <value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/>
+       <value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/>
+       <value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/>
+       <value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/>
+       <value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/>
+       <value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/>
+       <value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/>
+       <value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/>
+       <value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/>
+       <value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/>
+       <value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/>
+       <value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/>
+       <value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/>
+       <value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/>
+       <value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/>
+       <value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/>
+       <value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/>
+       <value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/>
+       <value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/>
+       <value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/>
+       <value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/>
+       <value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/>
+       <value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/>
+       <value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/>
+       <value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/>
+       <value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/>
+       <value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/>
+       <value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/>
+       <value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/>
+       <value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/>
+       <value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/>
+       <value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/>
+       <value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/>
+       <value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/>
+       <value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/>
+       <value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/>
+       <value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/>
+       <value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/>
+       <value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/>
+       <value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/>
+       <value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/>
+       <value value="72" name="PERF_PAPC_PASX_REC_IDLE"/>
+       <value value="73" name="PERF_PAPC_PASX_REC_BUSY"/>
+       <value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/>
+       <value value="75" name="PERF_PAPC_PASX_REC_STALLED"/>
+       <value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/>
+       <value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/>
+       <value value="78" name="PERF_PAPC_CCGSM_IDLE"/>
+       <value value="79" name="PERF_PAPC_CCGSM_BUSY"/>
+       <value value="80" name="PERF_PAPC_CCGSM_STALLED"/>
+       <value value="81" name="PERF_PAPC_CLPRIM_IDLE"/>
+       <value value="82" name="PERF_PAPC_CLPRIM_BUSY"/>
+       <value value="83" name="PERF_PAPC_CLPRIM_STALLED"/>
+       <value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/>
+       <value value="85" name="PERF_PAPC_CLIPSM_IDLE"/>
+       <value value="86" name="PERF_PAPC_CLIPSM_BUSY"/>
+       <value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/>
+       <value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/>
+       <value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/>
+       <value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/>
+       <value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/>
+       <value value="92" name="PERF_PAPC_CLIPGA_IDLE"/>
+       <value value="93" name="PERF_PAPC_CLIPGA_BUSY"/>
+       <value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/>
+       <value value="95" name="PERF_PAPC_CLIPGA_STALLED"/>
+       <value value="96" name="PERF_PAPC_CLIP_IDLE"/>
+       <value value="97" name="PERF_PAPC_CLIP_BUSY"/>
+       <value value="98" name="PERF_PAPC_SU_IDLE"/>
+       <value value="99" name="PERF_PAPC_SU_BUSY"/>
+       <value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/>
+       <value value="101" name="PERF_PAPC_SU_STALLED_SC"/>
+       <value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/>
+</enum>
+
+<enum name="a2xx_sc_perfcnt_select">
+       <value value="0" name="SC_SR_WINDOW_VALID"/>
+       <value value="1" name="SC_CW_WINDOW_VALID"/>
+       <value value="2" name="SC_QM_WINDOW_VALID"/>
+       <value value="3" name="SC_FW_WINDOW_VALID"/>
+       <value value="4" name="SC_EZ_WINDOW_VALID"/>
+       <value value="5" name="SC_IT_WINDOW_VALID"/>
+       <value value="6" name="SC_STARVED_BY_PA"/>
+       <value value="7" name="SC_STALLED_BY_RB_TILE"/>
+       <value value="8" name="SC_STALLED_BY_RB_SAMP"/>
+       <value value="9" name="SC_STARVED_BY_RB_EZ"/>
+       <value value="10" name="SC_STALLED_BY_SAMPLE_FF"/>
+       <value value="11" name="SC_STALLED_BY_SQ"/>
+       <value value="12" name="SC_STALLED_BY_SP"/>
+       <value value="13" name="SC_TOTAL_NO_PRIMS"/>
+       <value value="14" name="SC_NON_EMPTY_PRIMS"/>
+       <value value="15" name="SC_NO_TILES_PASSING_QM"/>
+       <value value="16" name="SC_NO_PIXELS_PRE_EZ"/>
+       <value value="17" name="SC_NO_PIXELS_POST_EZ"/>
+</enum>
+
+<enum name="a2xx_vgt_perfcount_select">
+       <value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
+       <value value="1" name="VGT_SQ_SEND"/>
+       <value value="2" name="VGT_SQ_STALLED"/>
+       <value value="3" name="VGT_SQ_STARVED_BUSY"/>
+       <value value="4" name="VGT_SQ_STARVED_IDLE"/>
+       <value value="5" name="VGT_SQ_STATIC"/>
+       <value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/>
+       <value value="7" name="VGT_PA_CLIP_V_SEND"/>
+       <value value="8" name="VGT_PA_CLIP_V_STALLED"/>
+       <value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/>
+       <value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/>
+       <value value="11" name="VGT_PA_CLIP_V_STATIC"/>
+       <value value="12" name="VGT_PA_CLIP_P_SEND"/>
+       <value value="13" name="VGT_PA_CLIP_P_STALLED"/>
+       <value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/>
+       <value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/>
+       <value value="16" name="VGT_PA_CLIP_P_STATIC"/>
+       <value value="17" name="VGT_PA_CLIP_S_SEND"/>
+       <value value="18" name="VGT_PA_CLIP_S_STALLED"/>
+       <value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/>
+       <value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/>
+       <value value="21" name="VGT_PA_CLIP_S_STATIC"/>
+       <value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/>
+       <value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/>
+       <value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/>
+       <value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/>
+       <value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/>
+       <value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/>
+       <value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/>
+       <value value="29" name="BIN_PRIM_NEAR_CULL"/>
+       <value value="30" name="BIN_PRIM_ZERO_CULL"/>
+       <value value="31" name="BIN_PRIM_FAR_CULL"/>
+       <value value="32" name="BIN_PRIM_BIN_CULL"/>
+       <value value="33" name="BIN_PRIM_FACE_CULL"/>
+       <value value="34" name="SPARE34"/>
+       <value value="35" name="SPARE35"/>
+       <value value="36" name="SPARE36"/>
+       <value value="37" name="SPARE37"/>
+       <value value="38" name="SPARE38"/>
+       <value value="39" name="SPARE39"/>
+       <value value="40" name="TE_SU_IN_VALID"/>
+       <value value="41" name="TE_SU_IN_READ"/>
+       <value value="42" name="TE_SU_IN_PRIM"/>
+       <value value="43" name="TE_SU_IN_EOP"/>
+       <value value="44" name="TE_SU_IN_NULL_PRIM"/>
+       <value value="45" name="TE_WK_IN_VALID"/>
+       <value value="46" name="TE_WK_IN_READ"/>
+       <value value="47" name="TE_OUT_PRIM_VALID"/>
+       <value value="48" name="TE_OUT_PRIM_READ"/>
+</enum>
+
+<enum name="a2xx_tcr_perfcount_select">
+       <value value="0" name="DGMMPD_IPMUX0_STALL"/>
+       <value value="4" name="DGMMPD_IPMUX_ALL_STALL"/>
+       <value value="5" name="OPMUX0_L2_WRITES"/>
+</enum>
+
+<enum name="a2xx_tp_perfcount_select">
+       <value value="0" name="POINT_QUADS"/>
+       <value value="1" name="BILIN_QUADS"/>
+       <value value="2" name="ANISO_QUADS"/>
+       <value value="3" name="MIP_QUADS"/>
+       <value value="4" name="VOL_QUADS"/>
+       <value value="5" name="MIP_VOL_QUADS"/>
+       <value value="6" name="MIP_ANISO_QUADS"/>
+       <value value="7" name="VOL_ANISO_QUADS"/>
+       <value value="8" name="ANISO_2_1_QUADS"/>
+       <value value="9" name="ANISO_4_1_QUADS"/>
+       <value value="10" name="ANISO_6_1_QUADS"/>
+       <value value="11" name="ANISO_8_1_QUADS"/>
+       <value value="12" name="ANISO_10_1_QUADS"/>
+       <value value="13" name="ANISO_12_1_QUADS"/>
+       <value value="14" name="ANISO_14_1_QUADS"/>
+       <value value="15" name="ANISO_16_1_QUADS"/>
+       <value value="16" name="MIP_VOL_ANISO_QUADS"/>
+       <value value="17" name="ALIGN_2_QUADS"/>
+       <value value="18" name="ALIGN_4_QUADS"/>
+       <value value="19" name="PIX_0_QUAD"/>
+       <value value="20" name="PIX_1_QUAD"/>
+       <value value="21" name="PIX_2_QUAD"/>
+       <value value="22" name="PIX_3_QUAD"/>
+       <value value="23" name="PIX_4_QUAD"/>
+       <value value="24" name="TP_MIPMAP_LOD0"/>
+       <value value="25" name="TP_MIPMAP_LOD1"/>
+       <value value="26" name="TP_MIPMAP_LOD2"/>
+       <value value="27" name="TP_MIPMAP_LOD3"/>
+       <value value="28" name="TP_MIPMAP_LOD4"/>
+       <value value="29" name="TP_MIPMAP_LOD5"/>
+       <value value="30" name="TP_MIPMAP_LOD6"/>
+       <value value="31" name="TP_MIPMAP_LOD7"/>
+       <value value="32" name="TP_MIPMAP_LOD8"/>
+       <value value="33" name="TP_MIPMAP_LOD9"/>
+       <value value="34" name="TP_MIPMAP_LOD10"/>
+       <value value="35" name="TP_MIPMAP_LOD11"/>
+       <value value="36" name="TP_MIPMAP_LOD12"/>
+       <value value="37" name="TP_MIPMAP_LOD13"/>
+       <value value="38" name="TP_MIPMAP_LOD14"/>
+</enum>
+
+<enum name="a2xx_tcm_perfcount_select">
+       <value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
+       <value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/>
+       <value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/>
+       <value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/>
+       <value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/>
+       <value value="28" name="READ_STARVED_QUAD0"/>
+       <value value="32" name="READ_STARVED"/>
+       <value value="33" name="READ_STALLED_QUAD0"/>
+       <value value="37" name="READ_STALLED"/>
+       <value value="38" name="VALID_READ_QUAD0"/>
+       <value value="42" name="TC_TP_STARVED_QUAD0"/>
+       <value value="46" name="TC_TP_STARVED"/>
+</enum>
+
+<enum name="a2xx_tcf_perfcount_select">
+       <value value="0" name="VALID_CYCLES"/>
+       <value value="1" name="SINGLE_PHASES"/>
+       <value value="2" name="ANISO_PHASES"/>
+       <value value="3" name="MIP_PHASES"/>
+       <value value="4" name="VOL_PHASES"/>
+       <value value="5" name="MIP_VOL_PHASES"/>
+       <value value="6" name="MIP_ANISO_PHASES"/>
+       <value value="7" name="VOL_ANISO_PHASES"/>
+       <value value="8" name="ANISO_2_1_PHASES"/>
+       <value value="9" name="ANISO_4_1_PHASES"/>
+       <value value="10" name="ANISO_6_1_PHASES"/>
+       <value value="11" name="ANISO_8_1_PHASES"/>
+       <value value="12" name="ANISO_10_1_PHASES"/>
+       <value value="13" name="ANISO_12_1_PHASES"/>
+       <value value="14" name="ANISO_14_1_PHASES"/>
+       <value value="15" name="ANISO_16_1_PHASES"/>
+       <value value="16" name="MIP_VOL_ANISO_PHASES"/>
+       <value value="17" name="ALIGN_2_PHASES"/>
+       <value value="18" name="ALIGN_4_PHASES"/>
+       <value value="19" name="TPC_BUSY"/>
+       <value value="20" name="TPC_STALLED"/>
+       <value value="21" name="TPC_STARVED"/>
+       <value value="22" name="TPC_WORKING"/>
+       <value value="23" name="TPC_WALKER_BUSY"/>
+       <value value="24" name="TPC_WALKER_STALLED"/>
+       <value value="25" name="TPC_WALKER_WORKING"/>
+       <value value="26" name="TPC_ALIGNER_BUSY"/>
+       <value value="27" name="TPC_ALIGNER_STALLED"/>
+       <value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/>
+       <value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/>
+       <value value="30" name="TPC_ALIGNER_WORKING"/>
+       <value value="31" name="TPC_BLEND_BUSY"/>
+       <value value="32" name="TPC_BLEND_SYNC"/>
+       <value value="33" name="TPC_BLEND_STARVED"/>
+       <value value="34" name="TPC_BLEND_WORKING"/>
+       <value value="35" name="OPCODE_0x00"/>
+       <value value="36" name="OPCODE_0x01"/>
+       <value value="37" name="OPCODE_0x04"/>
+       <value value="38" name="OPCODE_0x10"/>
+       <value value="39" name="OPCODE_0x11"/>
+       <value value="40" name="OPCODE_0x12"/>
+       <value value="41" name="OPCODE_0x13"/>
+       <value value="42" name="OPCODE_0x18"/>
+       <value value="43" name="OPCODE_0x19"/>
+       <value value="44" name="OPCODE_0x1A"/>
+       <value value="45" name="OPCODE_OTHER"/>
+       <value value="56" name="IN_FIFO_0_EMPTY"/>
+       <value value="57" name="IN_FIFO_0_LT_HALF_FULL"/>
+       <value value="58" name="IN_FIFO_0_HALF_FULL"/>
+       <value value="59" name="IN_FIFO_0_FULL"/>
+       <value value="72" name="IN_FIFO_TPC_EMPTY"/>
+       <value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/>
+       <value value="74" name="IN_FIFO_TPC_HALF_FULL"/>
+       <value value="75" name="IN_FIFO_TPC_FULL"/>
+       <value value="76" name="TPC_TC_XFC"/>
+       <value value="77" name="TPC_TC_STATE"/>
+       <value value="78" name="TC_STALL"/>
+       <value value="79" name="QUAD0_TAPS"/>
+       <value value="83" name="QUADS"/>
+       <value value="84" name="TCA_SYNC_STALL"/>
+       <value value="85" name="TAG_STALL"/>
+       <value value="88" name="TCB_SYNC_STALL"/>
+       <value value="89" name="TCA_VALID"/>
+       <value value="90" name="PROBES_VALID"/>
+       <value value="91" name="MISS_STALL"/>
+       <value value="92" name="FETCH_FIFO_STALL"/>
+       <value value="93" name="TCO_STALL"/>
+       <value value="94" name="ANY_STALL"/>
+       <value value="95" name="TAG_MISSES"/>
+       <value value="96" name="TAG_HITS"/>
+       <value value="97" name="SUB_TAG_MISSES"/>
+       <value value="98" name="SET0_INVALIDATES"/>
+       <value value="99" name="SET1_INVALIDATES"/>
+       <value value="100" name="SET2_INVALIDATES"/>
+       <value value="101" name="SET3_INVALIDATES"/>
+       <value value="102" name="SET0_TAG_MISSES"/>
+       <value value="103" name="SET1_TAG_MISSES"/>
+       <value value="104" name="SET2_TAG_MISSES"/>
+       <value value="105" name="SET3_TAG_MISSES"/>
+       <value value="106" name="SET0_TAG_HITS"/>
+       <value value="107" name="SET1_TAG_HITS"/>
+       <value value="108" name="SET2_TAG_HITS"/>
+       <value value="109" name="SET3_TAG_HITS"/>
+       <value value="110" name="SET0_SUB_TAG_MISSES"/>
+       <value value="111" name="SET1_SUB_TAG_MISSES"/>
+       <value value="112" name="SET2_SUB_TAG_MISSES"/>
+       <value value="113" name="SET3_SUB_TAG_MISSES"/>
+       <value value="114" name="SET0_EVICT1"/>
+       <value value="115" name="SET0_EVICT2"/>
+       <value value="116" name="SET0_EVICT3"/>
+       <value value="117" name="SET0_EVICT4"/>
+       <value value="118" name="SET0_EVICT5"/>
+       <value value="119" name="SET0_EVICT6"/>
+       <value value="120" name="SET0_EVICT7"/>
+       <value value="121" name="SET0_EVICT8"/>
+       <value value="130" name="SET1_EVICT1"/>
+       <value value="131" name="SET1_EVICT2"/>
+       <value value="132" name="SET1_EVICT3"/>
+       <value value="133" name="SET1_EVICT4"/>
+       <value value="134" name="SET1_EVICT5"/>
+       <value value="135" name="SET1_EVICT6"/>
+       <value value="136" name="SET1_EVICT7"/>
+       <value value="137" name="SET1_EVICT8"/>
+       <value value="146" name="SET2_EVICT1"/>
+       <value value="147" name="SET2_EVICT2"/>
+       <value value="148" name="SET2_EVICT3"/>
+       <value value="149" name="SET2_EVICT4"/>
+       <value value="150" name="SET2_EVICT5"/>
+       <value value="151" name="SET2_EVICT6"/>
+       <value value="152" name="SET2_EVICT7"/>
+       <value value="153" name="SET2_EVICT8"/>
+       <value value="162" name="SET3_EVICT1"/>
+       <value value="163" name="SET3_EVICT2"/>
+       <value value="164" name="SET3_EVICT3"/>
+       <value value="165" name="SET3_EVICT4"/>
+       <value value="166" name="SET3_EVICT5"/>
+       <value value="167" name="SET3_EVICT6"/>
+       <value value="168" name="SET3_EVICT7"/>
+       <value value="169" name="SET3_EVICT8"/>
+       <value value="178" name="FF_EMPTY"/>
+       <value value="179" name="FF_LT_HALF_FULL"/>
+       <value value="180" name="FF_HALF_FULL"/>
+       <value value="181" name="FF_FULL"/>
+       <value value="182" name="FF_XFC"/>
+       <value value="183" name="FF_STALLED"/>
+       <value value="184" name="FG_MASKS"/>
+       <value value="185" name="FG_LEFT_MASKS"/>
+       <value value="186" name="FG_LEFT_MASK_STALLED"/>
+       <value value="187" name="FG_LEFT_NOT_DONE_STALL"/>
+       <value value="188" name="FG_LEFT_FG_STALL"/>
+       <value value="189" name="FG_LEFT_SECTORS"/>
+       <value value="195" name="FG0_REQUESTS"/>
+       <value value="196" name="FG0_STALLED"/>
+       <value value="199" name="MEM_REQ512"/>
+       <value value="200" name="MEM_REQ_SENT"/>
+       <value value="202" name="MEM_LOCAL_READ_REQ"/>
+       <value value="203" name="TC0_MH_STALLED"/>
+</enum>
+
+<enum name="a2xx_sq_perfcnt_select">
+       <value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
+       <value value="1" name="SQ_VERTEX_VECTORS_SUB"/>
+       <value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/>
+       <value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/>
+       <value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/>
+       <value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/>
+       <value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/>
+       <value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/>
+       <value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/>
+       <value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/>
+       <value value="10" name="SQ_EXPORT_CYCLES"/>
+       <value value="11" name="SQ_ALU_CST_WRITTEN"/>
+       <value value="12" name="SQ_TEX_CST_WRITTEN"/>
+       <value value="13" name="SQ_ALU_CST_STALL"/>
+       <value value="14" name="SQ_ALU_TEX_STALL"/>
+       <value value="15" name="SQ_INST_WRITTEN"/>
+       <value value="16" name="SQ_BOOLEAN_WRITTEN"/>
+       <value value="17" name="SQ_LOOPS_WRITTEN"/>
+       <value value="18" name="SQ_PIXEL_SWAP_IN"/>
+       <value value="19" name="SQ_PIXEL_SWAP_OUT"/>
+       <value value="20" name="SQ_VERTEX_SWAP_IN"/>
+       <value value="21" name="SQ_VERTEX_SWAP_OUT"/>
+       <value value="22" name="SQ_ALU_VTX_INST_ISSUED"/>
+       <value value="23" name="SQ_TEX_VTX_INST_ISSUED"/>
+       <value value="24" name="SQ_VC_VTX_INST_ISSUED"/>
+       <value value="25" name="SQ_CF_VTX_INST_ISSUED"/>
+       <value value="26" name="SQ_ALU_PIX_INST_ISSUED"/>
+       <value value="27" name="SQ_TEX_PIX_INST_ISSUED"/>
+       <value value="28" name="SQ_VC_PIX_INST_ISSUED"/>
+       <value value="29" name="SQ_CF_PIX_INST_ISSUED"/>
+       <value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/>
+       <value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/>
+       <value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/>
+       <value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/>
+       <value value="34" name="SQ_ALU_NOPS"/>
+       <value value="35" name="SQ_PRED_SKIP"/>
+       <value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/>
+       <value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/>
+       <value value="38" name="SQ_SYNC_TEX_STALL_VTX"/>
+       <value value="39" name="SQ_SYNC_VC_STALL_VTX"/>
+       <value value="40" name="SQ_CONSTANTS_USED_SIMD0"/>
+       <value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/>
+       <value value="42" name="SQ_GPR_STALL_VTX"/>
+       <value value="43" name="SQ_GPR_STALL_PIX"/>
+       <value value="44" name="SQ_VTX_RS_STALL"/>
+       <value value="45" name="SQ_PIX_RS_STALL"/>
+       <value value="46" name="SQ_SX_PC_FULL"/>
+       <value value="47" name="SQ_SX_EXP_BUFF_FULL"/>
+       <value value="48" name="SQ_SX_POS_BUFF_FULL"/>
+       <value value="49" name="SQ_INTERP_QUADS"/>
+       <value value="50" name="SQ_INTERP_ACTIVE"/>
+       <value value="51" name="SQ_IN_PIXEL_STALL"/>
+       <value value="52" name="SQ_IN_VTX_STALL"/>
+       <value value="53" name="SQ_VTX_CNT"/>
+       <value value="54" name="SQ_VTX_VECTOR2"/>
+       <value value="55" name="SQ_VTX_VECTOR3"/>
+       <value value="56" name="SQ_VTX_VECTOR4"/>
+       <value value="57" name="SQ_PIXEL_VECTOR1"/>
+       <value value="58" name="SQ_PIXEL_VECTOR23"/>
+       <value value="59" name="SQ_PIXEL_VECTOR4"/>
+       <value value="60" name="SQ_CONSTANTS_USED_SIMD1"/>
+       <value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/>
+       <value value="62" name="SQ_SX_MEM_EXP_FULL"/>
+       <value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/>
+       <value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/>
+       <value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/>
+       <value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/>
+       <value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/>
+       <value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/>
+       <value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/>
+       <value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/>
+       <value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/>
+       <value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/>
+       <value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/>
+       <value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/>
+       <value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/>
+       <value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/>
+       <value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/>
+       <value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/>
+       <value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/>
+       <value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/>
+       <value value="81" name="SQ_SYNC_TEX_STALL_PIX"/>
+       <value value="82" name="SQ_SYNC_VC_STALL_PIX"/>
+       <value value="83" name="SQ_CONSTANTS_USED_SIMD2"/>
+       <value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/>
+       <value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/>
+       <value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/>
+       <value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/>
+       <value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/>
+       <value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/>
+       <value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/>
+       <value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/>
+       <value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/>
+       <value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/>
+       <value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/>
+       <value value="95" name="VC_PERF_STATIC"/>
+       <value value="96" name="VC_PERF_STALLED"/>
+       <value value="97" name="VC_PERF_STARVED"/>
+       <value value="98" name="VC_PERF_SEND"/>
+       <value value="99" name="VC_PERF_ACTUAL_STARVED"/>
+       <value value="100" name="PIXEL_THREAD_0_ACTIVE"/>
+       <value value="101" name="VERTEX_THREAD_0_ACTIVE"/>
+       <value value="102" name="PIXEL_THREAD_0_NUMBER"/>
+       <value value="103" name="VERTEX_THREAD_0_NUMBER"/>
+       <value value="104" name="VERTEX_EVENT_NUMBER"/>
+       <value value="105" name="PIXEL_EVENT_NUMBER"/>
+       <value value="106" name="PTRBUFF_EF_PUSH"/>
+       <value value="107" name="PTRBUFF_EF_POP_EVENT"/>
+       <value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/>
+       <value value="109" name="PTRBUFF_EF_POP_DEALLOC"/>
+       <value value="110" name="PTRBUFF_EF_POP_PVECTOR"/>
+       <value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/>
+       <value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/>
+       <value value="113" name="PTRBUFF_PB_DEALLOC"/>
+       <value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/>
+       <value value="115" name="PTRBUFF_PI_RTR"/>
+       <value value="116" name="PTRBUFF_PI_READ_EN"/>
+       <value value="117" name="PTRBUFF_PI_BUFF_SWAP"/>
+       <value value="118" name="PTRBUFF_SQ_FREE_BUFF"/>
+       <value value="119" name="PTRBUFF_SQ_DEC"/>
+       <value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/>
+       <value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/>
+       <value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/>
+       <value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/>
+       <value value="124" name="PTRBUFF_QUAL_EVENT"/>
+       <value value="125" name="PTRBUFF_END_BUFFER"/>
+       <value value="126" name="PTRBUFF_FILL_QUAD"/>
+       <value value="127" name="VERTS_WRITTEN_SPI"/>
+       <value value="128" name="TP_FETCH_INSTR_EXEC"/>
+       <value value="129" name="TP_FETCH_INSTR_REQ"/>
+       <value value="130" name="TP_DATA_RETURN"/>
+       <value value="131" name="SPI_WRITE_CYCLES_SP"/>
+       <value value="132" name="SPI_WRITES_SP"/>
+       <value value="133" name="SP_ALU_INSTR_EXEC"/>
+       <value value="134" name="SP_CONST_ADDR_TO_SQ"/>
+       <value value="135" name="SP_PRED_KILLS_TO_SQ"/>
+       <value value="136" name="SP_EXPORT_CYCLES_TO_SX"/>
+       <value value="137" name="SP_EXPORTS_TO_SX"/>
+       <value value="138" name="SQ_CYCLES_ELAPSED"/>
+       <value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/>
+       <value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/>
+       <value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/>
+       <value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/>
+       <value value="143" name="SQ_TCFS_ARB_XFC_CNT"/>
+       <value value="144" name="SQ_ALU0_ARB_XFC_CNT"/>
+       <value value="145" name="SQ_ALU1_ARB_XFC_CNT"/>
+       <value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/>
+       <value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/>
+       <value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/>
+       <value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/>
+       <value value="150" name="SQ_VTX_POP_THREAD_CNT"/>
+       <value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/>
+       <value value="152" name="SQ_PIX_POP_THREAD_CNT"/>
+       <value value="153" name="SQ_PIX_TOTAL"/>
+       <value value="154" name="SQ_PIX_KILLED"/>
+</enum>
+
+<enum name="a2xx_sx_perfcnt_select">
+       <value value="0" name="SX_EXPORT_VECTORS"/>
+       <value value="1" name="SX_DUMMY_QUADS"/>
+       <value value="2" name="SX_ALPHA_FAIL"/>
+       <value value="3" name="SX_RB_QUAD_BUSY"/>
+       <value value="4" name="SX_RB_COLOR_BUSY"/>
+       <value value="5" name="SX_RB_QUAD_STALL"/>
+       <value value="6" name="SX_RB_COLOR_STALL"/>
+</enum>
+
+<enum name="a2xx_rbbm_perfcount1_sel">
+       <value value="0" name="RBBM1_COUNT"/>
+       <value value="1" name="RBBM1_NRT_BUSY"/>
+       <value value="2" name="RBBM1_RB_BUSY"/>
+       <value value="3" name="RBBM1_SQ_CNTX0_BUSY"/>
+       <value value="4" name="RBBM1_SQ_CNTX17_BUSY"/>
+       <value value="5" name="RBBM1_VGT_BUSY"/>
+       <value value="6" name="RBBM1_VGT_NODMA_BUSY"/>
+       <value value="7" name="RBBM1_PA_BUSY"/>
+       <value value="8" name="RBBM1_SC_CNTX_BUSY"/>
+       <value value="9" name="RBBM1_TPC_BUSY"/>
+       <value value="10" name="RBBM1_TC_BUSY"/>
+       <value value="11" name="RBBM1_SX_BUSY"/>
+       <value value="12" name="RBBM1_CP_COHER_BUSY"/>
+       <value value="13" name="RBBM1_CP_NRT_BUSY"/>
+       <value value="14" name="RBBM1_GFX_IDLE_STALL"/>
+       <value value="15" name="RBBM1_INTERRUPT"/>
+</enum>
+
+<enum name="a2xx_cp_perfcount_sel">
+       <value value="0" name="ALWAYS_COUNT"/>
+       <value value="1" name="TRANS_FIFO_FULL"/>
+       <value value="2" name="TRANS_FIFO_AF"/>
+       <value value="3" name="RCIU_PFPTRANS_WAIT"/>
+       <value value="6" name="RCIU_NRTTRANS_WAIT"/>
+       <value value="8" name="CSF_NRT_READ_WAIT"/>
+       <value value="9" name="CSF_I1_FIFO_FULL"/>
+       <value value="10" name="CSF_I2_FIFO_FULL"/>
+       <value value="11" name="CSF_ST_FIFO_FULL"/>
+       <value value="13" name="CSF_RING_ROQ_FULL"/>
+       <value value="14" name="CSF_I1_ROQ_FULL"/>
+       <value value="15" name="CSF_I2_ROQ_FULL"/>
+       <value value="16" name="CSF_ST_ROQ_FULL"/>
+       <value value="18" name="MIU_TAG_MEM_FULL"/>
+       <value value="19" name="MIU_WRITECLEAN"/>
+       <value value="22" name="MIU_NRT_WRITE_STALLED"/>
+       <value value="23" name="MIU_NRT_READ_STALLED"/>
+       <value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/>
+       <value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/>
+       <value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/>
+       <value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/>
+       <value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/>
+       <value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/>
+       <value value="30" name="ME_MICRO_RB_STARVED"/>
+       <value value="31" name="ME_MICRO_I1_STARVED"/>
+       <value value="32" name="ME_MICRO_I2_STARVED"/>
+       <value value="33" name="ME_MICRO_ST_STARVED"/>
+       <value value="40" name="RCIU_RBBM_DWORD_SENT"/>
+       <value value="41" name="ME_BUSY_CLOCKS"/>
+       <value value="42" name="ME_WAIT_CONTEXT_AVAIL"/>
+       <value value="43" name="PFP_TYPE0_PACKET"/>
+       <value value="44" name="PFP_TYPE3_PACKET"/>
+       <value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/>
+       <value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/>
+       <value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/>
+       <value value="48" name="CSF_RBI1I2_FETCHING"/>
+</enum>
+
+<enum name="a2xx_rb_perfcnt_select">
+       <value value="0" name="RBPERF_CNTX_BUSY"/>
+       <value value="1" name="RBPERF_CNTX_BUSY_MAX"/>
+       <value value="2" name="RBPERF_SX_QUAD_STARVED"/>
+       <value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/>
+       <value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/>
+       <value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/>
+       <value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/>
+       <value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/>
+       <value value="8" name="RBPERF_MH_STARVED"/>
+       <value value="9" name="RBPERF_MH_STARVED_MAX"/>
+       <value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/>
+       <value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/>
+       <value value="12" name="RBPERF_AZ_BC_Z_BUSY"/>
+       <value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/>
+       <value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/>
+       <value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/>
+       <value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/>
+       <value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/>
+       <value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/>
+       <value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/>
+       <value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/>
+       <value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/>
+       <value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/>
+       <value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/>
+       <value value="24" name="RBPERF_ZXP_STALL"/>
+       <value value="25" name="RBPERF_ZXP_STALL_MAX"/>
+       <value value="26" name="RBPERF_EVENT_PENDING"/>
+       <value value="27" name="RBPERF_EVENT_PENDING_MAX"/>
+       <value value="28" name="RBPERF_RB_MH_VALID"/>
+       <value value="29" name="RBPERF_RB_MH_VALID_MAX"/>
+       <value value="30" name="RBPERF_SX_RB_QUAD_SEND"/>
+       <value value="31" name="RBPERF_SX_RB_COLOR_SEND"/>
+       <value value="32" name="RBPERF_SC_RB_TILE_SEND"/>
+       <value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/>
+       <value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/>
+       <value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/>
+       <value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/>
+       <value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/>
+       <value value="38" name="RBPERF_RB_SC_EZ_SEND"/>
+       <value value="39" name="RBPERF_RB_SX_INDEX_SEND"/>
+       <value value="40" name="RBPERF_GMEM_INTFO_RD"/>
+       <value value="41" name="RBPERF_GMEM_INTF1_RD"/>
+       <value value="42" name="RBPERF_GMEM_INTFO_WR"/>
+       <value value="43" name="RBPERF_GMEM_INTF1_WR"/>
+       <value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/>
+       <value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/>
+       <value value="46" name="RBPERF_ZPASS_DONE"/>
+       <value value="47" name="RBPERF_ZCMD_VALID"/>
+       <value value="48" name="RBPERF_CCMD_VALID"/>
+       <value value="49" name="RBPERF_ACCUM_GRANT"/>
+       <value value="50" name="RBPERF_ACCUM_C0_GRANT"/>
+       <value value="51" name="RBPERF_ACCUM_C1_GRANT"/>
+       <value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/>
+       <value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/>
+       <value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/>
+       <value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/>
+       <value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
+</enum>
+
+<domain name="A2XX" width="32">
+
+       <bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
+               <bitfield name="COLUMN" low="0" high="2" type="uint"/>
+               <bitfield name="ROW" low="3" high="5" type="uint"/>
+               <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
+       </bitset>
+
+       <reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
+       <reg32 offset="0x003b" name="RBBM_CNTL"/>
+       <reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
+       <reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
+       <reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
+
+       <enum name="adreno_mmu_clnt_beh">
+               <value name="BEH_NEVR" value="0"/>
+               <value name="BEH_TRAN_RNG" value="1"/>
+               <value name="BEH_TRAN_FLT" value="2"/>
+       </enum>
+
+       <!--
+               Note: these seem applicable only for a2xx devices with gpummu?  At
+               any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
+               it doesn't make sense, so I think offset 0x40 must be a different
+               register on a3xx.. so moving this back into A2XX domain:
+        -->
+       <reg32 offset="0x0040" name="MH_MMU_CONFIG">
+               <bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
+               <bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
+               <bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/>
+               <bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/>
+       </reg32>
+       <reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
+               <bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
+               <bitfield name="VA_BASE" low="12" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
+       <reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
+       <reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
+       <reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
+               <bitfield name="INVALIDATE_ALL" pos="0"/>
+               <bitfield name="INVALIDATE_TC" pos="1"/>
+       </reg32>
+       <reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
+       <reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
+
+       <reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
+       <reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/>
+       <reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x039b" name="RBBM_DEBUG"/>
+       <reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
+               <bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0"/>
+               <bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1"/>
+               <bitfield name="SC_SCLK_PM_OVERRIDE" pos="2"/>
+               <bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3"/>
+               <bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4"/>
+               <bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5"/>
+               <bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6"/>
+               <bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7"/>
+               <bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8"/>
+               <bitfield name="SX_SCLK_PM_OVERRIDE" pos="9"/>
+               <bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10"/>
+               <bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11"/>
+               <bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12"/>
+               <bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13"/>
+               <bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14"/>
+               <bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15"/>
+               <bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16"/>
+               <bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17"/>
+               <bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18"/>
+               <bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19"/>
+               <bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20"/>
+               <bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21"/>
+               <bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22"/>
+               <bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23"/>
+               <bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24"/>
+               <bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25"/>
+               <bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26"/>
+               <bitfield name="RB_SCLK_PM_OVERRIDE" pos="27"/>
+               <bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28"/>
+               <bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29"/>
+               <bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30"/>
+               <bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31"/>
+       </reg32>
+       <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
+       <reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
+       <reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
+       <reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
+       <reg32 offset="0x03b4" name="RBBM_INT_CNTL">
+               <bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
+               <bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/>
+               <bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
+       <reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
+       <reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
+               <bitfield name="MH_INT_STAT" pos="5" type="boolean"/>
+               <bitfield name="SQ_INT_STAT" pos="26" type="boolean"/>
+               <bitfield name="CP_INT_STAT" pos="30" type="boolean"/>
+               <bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
+       <reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
+       <reg32 offset="0x0444" name="CP_PERFMON_CNTL"/>
+       <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
+       <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
+       <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
+       <reg32 offset="0x05d0" name="RBBM_STATUS">
+               <bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
+               <bitfield name="TC_BUSY" pos="5" type="boolean"/>
+               <bitfield name="HIRQ_PENDING" pos="8" type="boolean"/>
+               <bitfield name="CPRQ_PENDING" pos="9" type="boolean"/>
+               <bitfield name="CFRQ_PENDING" pos="10" type="boolean"/>
+               <bitfield name="PFRQ_PENDING" pos="11" type="boolean"/>
+               <bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/>
+               <bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/>
+               <bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/>
+               <bitfield name="MH_BUSY" pos="18" type="boolean"/>
+               <bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/>
+               <bitfield name="SX_BUSY" pos="21" type="boolean"/>
+               <bitfield name="TPC_BUSY" pos="22" type="boolean"/>
+               <bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/>
+               <bitfield name="PA_BUSY" pos="25" type="boolean"/>
+               <bitfield name="VGT_BUSY" pos="26" type="boolean"/>
+               <bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/>
+               <bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/>
+               <bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/>
+               <bitfield name="GUI_ACTIVE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
+               <bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
+               <bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/>
+               <bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/>
+               <bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/>
+               <bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/>
+               <bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/>
+               <bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/>
+               <bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/>
+               <bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/>
+               <bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/>
+               <bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/>
+               <bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/>
+               <bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/>
+               <bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/>
+               <bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
+               <bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
+               <bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/>
+               <bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
+       <reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
+       <reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
+       <reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
+       <reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
+               <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
+               <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
+       </reg32>
+       <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
+               <reg32 offset="0x0" name="CONFIG"/>
+               <reg32 offset="0x1" name="DATA_ADDRESS"/>
+               <reg32 offset="0x2" name="DATA_LENGTH"/>
+       </array>
+       <reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
+       <reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
+       <reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
+       <reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
+       <reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
+       <reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
+       <reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
+       <reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
+               <bitfield name="BASE_ADDR" low="5" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
+               <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
+               <bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/>
+               <bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/>
+       </reg32>
+       <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
+       <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
+               <bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
+               <bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/>
+       </reg32>
+       <reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
+       <reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
+       <reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
+       <reg32 offset="0x0d36" name="SQ_INT_ACK"/>
+       <reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
+       <reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
+       <reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
+       <reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
+       <reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
+       <reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
+       <reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
+       <reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
+       <reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
+       <reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
+       <reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
+       <reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
+       <reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
+       <reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
+       <reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
+       <reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
+       <reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
+       <reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
+       <reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
+       <reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
+       <reg32 offset="0x0e00" name="TC_CNTL_STATUS">
+               <bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
+       <reg32 offset="0x0f01" name="RB_BC_CONTROL">
+               <bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
+               <bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/>
+               <bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/>
+               <bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/>
+               <bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/>
+               <bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/>
+               <bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/>
+               <bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/>
+               <bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/>
+               <bitfield name="CRC_MODE" pos="15" type="boolean"/>
+               <bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/>
+               <bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/>
+               <bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/>
+               <bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/>
+               <bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/>
+               <bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/>
+               <bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/>
+               <bitfield name="CRC_SYSTEM" pos="30" type="boolean"/>
+               <bitfield name="RESERVED6" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
+       <reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
+       <reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
+       <reg32 offset="0x2000" name="RB_SURFACE_INFO">
+               <bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
+               <bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2001" name="RB_COLOR_INFO">
+               <bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
+               <bitfield name="ROUND_MODE" low="4" high="5" type="uint"/>
+               <bitfield name="LINEAR" pos="6" type="boolean"/>
+               <bitfield name="ENDIAN" low="7" high="8" type="uint"/>
+               <bitfield name="SWAP" low="9" high="10" type="uint"/>
+               <bitfield name="BASE" low="12" high="31" shr="12"/>
+       </reg32>
+       <reg32 offset="0x2002" name="RB_DEPTH_INFO">
+               <bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
+               <bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/>
+       </reg32>
+       <reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
+       <reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
+       <reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
+       <reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
+       <reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
+               <bitfield name="X" low="0" high="14" type="int"/>
+               <bitfield name="Y" low="16" high="30" type="int"/>
+               <bitfield name="DISABLE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+       <reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+       <reg32 offset="0x2010" name="UNKNOWN_2010"/>
+       <reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
+       <reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
+       <reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
+       <reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
+       <reg32 offset="0x2104" name="RB_COLOR_MASK">
+               <bitfield name="WRITE_RED" pos="0" type="boolean"/>
+               <bitfield name="WRITE_GREEN" pos="1" type="boolean"/>
+               <bitfield name="WRITE_BLUE" pos="2" type="boolean"/>
+               <bitfield name="WRITE_ALPHA" pos="3" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2105" name="RB_BLEND_RED"/>
+       <reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
+       <reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
+       <reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
+       <reg32 offset="0x2109" name="RB_FOG_COLOR">
+               <bitfield name="FOG_RED" low="0" high="7" type="uint"/>
+               <bitfield name="FOG_GREEN" low="8" high="15" type="uint"/>
+               <bitfield name="FOG_BLUE" low="16" high="23" type="uint"/>
+       </reg32>
+       <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+       <reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+       <reg32 offset="0x210e" name="RB_ALPHA_REF"/>
+       <reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
+       <reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
+       <reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
+       <reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
+       <reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
+       <reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
+       <reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
+               <doc>
+                       note: only 0x3f worth of valid register values for VS_REGS and
+                       PS_REGS, but high bit is set to indicate '0 registers used':
+               </doc>
+               <bitfield name="VS_REGS" low="0" high="7" type="uint"/>
+               <bitfield name="PS_REGS" low="8" high="15" type="uint"/>
+               <bitfield name="VS_RESOURCE" pos="16" type="boolean"/>
+               <bitfield name="PS_RESOURCE" pos="17" type="boolean"/>
+               <bitfield name="PARAM_GEN" pos="18" type="boolean"/>
+               <bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/>
+               <bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/>
+               <bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/>
+               <bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/>
+               <bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
+               <bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
+               <bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/>
+               <bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/>
+               <bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/>
+               <bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/>
+               <bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/>
+               <bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
+               <bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
+               <bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2183" name="SQ_WRAPPING_0">
+               <bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
+               <bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/>
+               <bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/>
+               <bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/>
+               <bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/>
+               <bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/>
+               <bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/>
+               <bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2184" name="SQ_WRAPPING_1">
+               <bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
+               <bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/>
+               <bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/>
+               <bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/>
+               <bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/>
+               <bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/>
+               <bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/>
+               <bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
+               <bitfield name="BASE" low="0" high="11" type="uint"/>
+               <bitfield name="SIZE" low="12" high="23" type="uint"/>
+       </reg32>
+       <reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
+               <bitfield name="BASE" low="0" high="11" type="uint"/>
+               <bitfield name="SIZE" low="12" high="23" type="uint"/>
+       </reg32>
+       <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
+       <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
+       <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
+       <reg32 offset="0x2200" name="RB_DEPTHCONTROL">
+               <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+               <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
+               <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
+               <bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/>
+               <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
+               <bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/>
+               <bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/>
+               <bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/>
+               <bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/>
+               <bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+               <bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+               <bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+               <bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+               <bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+       </reg32>
+       <reg32 offset="0x2201" name="RB_BLEND_CONTROL">
+               <bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
+               <bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/>
+               <bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/>
+               <bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/>
+               <bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/>
+               <bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/>
+               <bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/>
+               <bitfield name="BLEND_FORCE" pos="30" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2202" name="RB_COLORCONTROL">
+               <bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
+               <bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/>
+               <bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/>
+               <bitfield name="BLEND_DISABLE" pos="5" type="boolean"/>
+               <bitfield name="VOB_ENABLE" pos="6" type="boolean"/>
+               <bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/>
+               <bitfield name="ROP_CODE" low="8" high="11" type="uint"/>
+               <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
+               <bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/>
+               <bitfield name="PIXEL_FOG" pos="16" type="boolean"/>
+               <bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/>
+               <bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/>
+               <bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/>
+               <bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
+       <reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
+               <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
+               <bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/>
+               <bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/>
+               <bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/>
+               <bitfield name="VTX_KILL_OR" pos="21" type="boolean"/>
+               <bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/>
+               <bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/>
+               <bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
+               <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+               <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+               <bitfield name="FACE" pos="2" type="boolean"/>
+               <bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/>
+               <bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
+               <bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
+               <bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/>
+               <bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/>
+               <bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/>
+               <bitfield name="MSAA_ENABLE" pos="15" type="boolean"/>
+               <bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/>
+               <bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/>
+               <bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/>
+               <bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/>
+               <bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/>
+               <bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/>
+               <bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/>
+               <bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/>
+               <bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/>
+               <bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/>
+               <bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/>
+               <bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
+               <bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
+               <bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/>
+               <bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/>
+               <bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/>
+               <bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/>
+               <bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/>
+               <bitfield name="VTX_XY_FMT" pos="8" type="boolean"/>
+               <bitfield name="VTX_Z_FMT" pos="9" type="boolean"/>
+               <bitfield name="VTX_W0_FMT" pos="10" type="boolean"/>
+               <bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
+       <reg32 offset="0x2208" name="RB_MODECONTROL">
+               <bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
+       </reg32>
+       <reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
+       <reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
+       <reg32 offset="0x220b" name="CLEAR_COLOR">
+               <bitfield name="RED" low="0" high="7"/>
+               <bitfield name="GREEN" low="8" high="15"/>
+               <bitfield name="BLUE" low="16" high="23"/>
+               <bitfield name="ALPHA" low="24" high="31"/>
+       </reg32>
+       <reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
+       <reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
+               <bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
+               <bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/>
+       </reg32>
+       <reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
+               <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+               <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+       </reg32>
+       <reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
+               <bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
+       </reg32>
+       <reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
+               <bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
+               <bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/>
+               <bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/>
+               <bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/>
+       </reg32>
+       <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
+               <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
+               <bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/>
+               <bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2294" name="VGT_ENHANCE"/>
+       <reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
+               <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
+               <bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/>
+               <bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/>
+               <bitfield name="LAST_PIXEL" pos="10" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
+               <bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
+               <bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
+               <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
+               <bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/>
+               <bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/>
+       </reg32>
+       <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
+       <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
+       <reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
+       <reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
+       <reg32 offset="0x2307" name="SQ_VS_CONST">
+               <bitfield name="BASE" low="0" high="8" type="uint"/>
+               <bitfield name="SIZE" low="12" high="20" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2308" name="SQ_PS_CONST">
+               <bitfield name="BASE" low="0" high="8" type="uint"/>
+               <bitfield name="SIZE" low="12" high="20" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
+       <reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
+       <reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
+       <reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
+               <bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
+               <bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2318" name="RB_COPY_CONTROL">
+               <bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
+               <bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/>
+               <bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/>
+       </reg32>
+       <reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
+       <reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
+       <reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
+               <bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
+               <bitfield name="LINEAR" pos="3" type="boolean"/>
+               <bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/>
+               <bitfield name="SWAP" low="8" high="9" type="uint"/>
+               <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
+               <bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/>
+               <bitfield name="WRITE_RED" pos="14" type="boolean"/>
+               <bitfield name="WRITE_GREEN" pos="15" type="boolean"/>
+               <bitfield name="WRITE_BLUE" pos="16" type="boolean"/>
+               <bitfield name="WRITE_ALPHA" pos="17" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
+               <bitfield name="X" low="0" high="12" type="uint"/>
+               <bitfield name="Y" low="13" high="25" type="uint"/>
+       </reg32>
+       <reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
+       <reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
+       <reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
+       <reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
+       <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
+       <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
+       <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
+       <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
+       <reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
+       <reg32 offset="0x4800" name="SQ_FETCH_0"/>
+       <reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
+       <reg32 offset="0x4908" name="SQ_CF_LOOP"/>
+       <reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
+       <reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
+       <reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
+
+       <reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
+       <reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
+       <reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
+       <reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
+       <reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
+       <reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
+       <reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
+       <reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
+       <reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
+       <reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
+       <reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
+       <reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
+       <reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
+       <reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
+       <reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
+       <reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
+       <reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
+       <reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
+       <reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
+       <reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
+       <reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
+       <reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
+       <reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
+       <reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
+       <reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
+       <reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
+       <reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
+       <reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
+       <reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
+       <reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
+       <reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
+       <reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
+       <reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
+       <reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
+       <reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
+       <reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
+       <reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
+       <reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
+       <reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
+       <reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
+       <reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
+       <reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
+       <reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
+       <reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
+       <reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
+       <reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
+       <reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
+       <reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
+       <reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
+       <reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
+       <reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
+       <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
+       <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/>
+       <reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/>
+       <reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/>
+       <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
+       <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
+       <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
+       <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
+       <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
+       <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
+</domain>
+
+<domain name="A2XX_SQ_TEX" width="32">
+       <doc>Texture state dwords</doc>
+       <enum name="sq_tex_clamp">
+               <value name="SQ_TEX_WRAP" value="0"/>
+               <value name="SQ_TEX_MIRROR" value="1"/>
+               <value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/>
+               <value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/>
+               <value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/>
+               <value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/>
+               <value name="SQ_TEX_CLAMP_BORDER" value="6"/>
+               <value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/>
+       </enum>
+       <enum name="sq_tex_swiz">
+               <value name="SQ_TEX_X" value="0"/>
+               <value name="SQ_TEX_Y" value="1"/>
+               <value name="SQ_TEX_Z" value="2"/>
+               <value name="SQ_TEX_W" value="3"/>
+               <value name="SQ_TEX_ZERO" value="4"/>
+               <value name="SQ_TEX_ONE" value="5"/>
+       </enum>
+       <enum name="sq_tex_filter">
+               <value name="SQ_TEX_FILTER_POINT" value="0"/>
+               <value name="SQ_TEX_FILTER_BILINEAR" value="1"/>
+               <value name="SQ_TEX_FILTER_BASEMAP" value="2"/>
+               <value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/>
+       </enum>
+       <enum name="sq_tex_aniso_filter">
+               <value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
+               <value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/>
+               <value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/>
+               <value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/>
+               <value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/>
+               <value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/>
+               <value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/>
+       </enum>
+       <enum name="sq_tex_dimension">
+               <value name="SQ_TEX_DIMENSION_1D" value="0"/>
+               <value name="SQ_TEX_DIMENSION_2D" value="1"/>
+               <value name="SQ_TEX_DIMENSION_3D" value="2"/>
+               <value name="SQ_TEX_DIMENSION_CUBE" value="3"/>
+       </enum>
+       <enum name="sq_tex_border_color">
+               <value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
+               <value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/>
+               <value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/>
+               <value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
+       </enum>
+       <enum name="sq_tex_sign">
+               <value name="SQ_TEX_SIGN_UNISIGNED" value="0"/>
+               <value name="SQ_TEX_SIGN_SIGNED" value="1"/>
+               <!-- biased: 2*color-1 (range -1,1 when sampling) -->
+               <value name="SQ_TEX_SIGN_UNISIGNED_BIASED" value="2"/>
+               <!-- gamma: sRGB to linear? -->
+               <value name="SQ_TEX_SIGN_GAMMA" value="3"/>
+       </enum>
+       <enum name="sq_tex_endian">
+               <value name="SQ_TEX_ENDIAN_NONE" value="0"/>
+               <value name="SQ_TEX_ENDIAN_8IN16" value="1"/>
+               <value name="SQ_TEX_ENDIAN_8IN32" value="2"/>
+               <value name="SQ_TEX_ENDIAN_16IN32" value="3"/>
+       </enum>
+       <enum name="sq_tex_clamp_policy">
+               <value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
+               <value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/>
+       </enum>
+       <enum name="sq_tex_num_format">
+               <value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
+               <value name="SQ_TEX_NUM_FORMAT_INT" value="1"/>
+       </enum>
+       <enum name="sq_tex_type">
+       <value name="SQ_TEX_TYPE_0" value="0"/>
+       <value name="SQ_TEX_TYPE_1" value="1"/>
+       <value name="SQ_TEX_TYPE_2" value="2"/>
+       <value name="SQ_TEX_TYPE_3" value="3"/>
+       </enum>
+       <reg32 offset="0" name="0">
+               <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
+               <bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/>
+               <bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/>
+               <bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/>
+               <bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/>
+               <bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/>
+               <bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>"
+               <bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>"
+               <bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
+               <bitfield name="TILED" pos="1" type="boolean"/>
+       </reg32>
+       <reg32 offset="1" name="1">
+               <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
+               <bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/>
+               <bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/>
+               <bitfield name="STACKED" pos="10" type="boolean"/>
+               <bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/>
+               <bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/>
+       </reg32>
+       <reg32 offset="2" name="2">
+               <bitfield name="WIDTH" low="0" high="12" type="uint"/>
+               <bitfield name="HEIGHT" low="13" high="25" type="uint"/>
+               <bitfield name="DEPTH" low="26" high="31" type="uint"/>
+               <!-- 1d/3d have different bit configurations -->
+       </reg32>
+       <reg32 offset="3" name="3">
+               <bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
+               <bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/>
+               <bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
+               <bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
+               <bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
+               <bitfield name="EXP_ADJUST" low="13" high="18" type="uint"/>
+               <bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
+               <bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
+               <bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
+               <bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/>
+               <bitfield name="BORDER_SIZE" pos="31" type="uint"/>
+       </reg32>
+       <reg32 offset="4" name="4">
+               <bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
+               <bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/>
+               <bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/>
+               <bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/>
+               <bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/>
+               <bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/>
+               <bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/>
+               <bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/>
+               <bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="5" name="5">
+               <bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
+               <bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/>
+               <bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/>
+               <bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->
+               <bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/>
+               <bitfield name="PACKED_MIPS" pos="11" type="boolean"/>
+               <bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/>
+       </reg32>
+</domain>
+
+</database>
diff --git a/src/freedreno/registers/a2xx.xml.h b/src/freedreno/registers/a2xx.xml.h
deleted file mode 100644 (file)
index deded78..0000000
+++ /dev/null
@@ -1,3017 +0,0 @@
-#ifndef A2XX_XML
-#define A2XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-01-21 14:36:17)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43561 bytes, from 2019-06-10 13:39:33)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  84030 bytes, from 2019-07-01 13:05:23)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147548 bytes, from 2019-06-10 13:39:33)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 152605 bytes, from 2019-07-01 13:13:03)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
-
-Copyright (C) 2013-2019 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum a2xx_rb_dither_type {
-       DITHER_PIXEL = 0,
-       DITHER_SUBPIXEL = 1,
-};
-
-enum a2xx_colorformatx {
-       COLORX_4_4_4_4 = 0,
-       COLORX_1_5_5_5 = 1,
-       COLORX_5_6_5 = 2,
-       COLORX_8 = 3,
-       COLORX_8_8 = 4,
-       COLORX_8_8_8_8 = 5,
-       COLORX_S8_8_8_8 = 6,
-       COLORX_16_FLOAT = 7,
-       COLORX_16_16_FLOAT = 8,
-       COLORX_16_16_16_16_FLOAT = 9,
-       COLORX_32_FLOAT = 10,
-       COLORX_32_32_FLOAT = 11,
-       COLORX_32_32_32_32_FLOAT = 12,
-       COLORX_2_3_3 = 13,
-       COLORX_8_8_8 = 14,
-};
-
-enum a2xx_sq_surfaceformat {
-       FMT_1_REVERSE = 0,
-       FMT_1 = 1,
-       FMT_8 = 2,
-       FMT_1_5_5_5 = 3,
-       FMT_5_6_5 = 4,
-       FMT_6_5_5 = 5,
-       FMT_8_8_8_8 = 6,
-       FMT_2_10_10_10 = 7,
-       FMT_8_A = 8,
-       FMT_8_B = 9,
-       FMT_8_8 = 10,
-       FMT_Cr_Y1_Cb_Y0 = 11,
-       FMT_Y1_Cr_Y0_Cb = 12,
-       FMT_5_5_5_1 = 13,
-       FMT_8_8_8_8_A = 14,
-       FMT_4_4_4_4 = 15,
-       FMT_8_8_8 = 16,
-       FMT_DXT1 = 18,
-       FMT_DXT2_3 = 19,
-       FMT_DXT4_5 = 20,
-       FMT_10_10_10_2 = 21,
-       FMT_24_8 = 22,
-       FMT_16 = 24,
-       FMT_16_16 = 25,
-       FMT_16_16_16_16 = 26,
-       FMT_16_EXPAND = 27,
-       FMT_16_16_EXPAND = 28,
-       FMT_16_16_16_16_EXPAND = 29,
-       FMT_16_FLOAT = 30,
-       FMT_16_16_FLOAT = 31,
-       FMT_16_16_16_16_FLOAT = 32,
-       FMT_32 = 33,
-       FMT_32_32 = 34,
-       FMT_32_32_32_32 = 35,
-       FMT_32_FLOAT = 36,
-       FMT_32_32_FLOAT = 37,
-       FMT_32_32_32_32_FLOAT = 38,
-       FMT_ATI_TC_RGB = 39,
-       FMT_ATI_TC_RGBA = 40,
-       FMT_ATI_TC_555_565_RGB = 41,
-       FMT_ATI_TC_555_565_RGBA = 42,
-       FMT_ATI_TC_RGBA_INTERP = 43,
-       FMT_ATI_TC_555_565_RGBA_INTERP = 44,
-       FMT_ETC1_RGBA_INTERP = 46,
-       FMT_ETC1_RGB = 47,
-       FMT_ETC1_RGBA = 48,
-       FMT_DXN = 49,
-       FMT_2_3_3 = 51,
-       FMT_2_10_10_10_AS_16_16_16_16 = 54,
-       FMT_10_10_10_2_AS_16_16_16_16 = 55,
-       FMT_32_32_32_FLOAT = 57,
-       FMT_DXT3A = 58,
-       FMT_DXT5A = 59,
-       FMT_CTX1 = 60,
-};
-
-enum a2xx_sq_ps_vtx_mode {
-       POSITION_1_VECTOR = 0,
-       POSITION_2_VECTORS_UNUSED = 1,
-       POSITION_2_VECTORS_SPRITE = 2,
-       POSITION_2_VECTORS_EDGE = 3,
-       POSITION_2_VECTORS_KILL = 4,
-       POSITION_2_VECTORS_SPRITE_KILL = 5,
-       POSITION_2_VECTORS_EDGE_KILL = 6,
-       MULTIPASS = 7,
-};
-
-enum a2xx_sq_sample_cntl {
-       CENTROIDS_ONLY = 0,
-       CENTERS_ONLY = 1,
-       CENTROIDS_AND_CENTERS = 2,
-};
-
-enum a2xx_dx_clip_space {
-       DXCLIP_OPENGL = 0,
-       DXCLIP_DIRECTX = 1,
-};
-
-enum a2xx_pa_su_sc_polymode {
-       POLY_DISABLED = 0,
-       POLY_DUALMODE = 1,
-};
-
-enum a2xx_rb_edram_mode {
-       EDRAM_NOP = 0,
-       COLOR_DEPTH = 4,
-       DEPTH_ONLY = 5,
-       EDRAM_COPY = 6,
-};
-
-enum a2xx_pa_sc_pattern_bit_order {
-       LITTLE = 0,
-       BIG = 1,
-};
-
-enum a2xx_pa_sc_auto_reset_cntl {
-       NEVER = 0,
-       EACH_PRIMITIVE = 1,
-       EACH_PACKET = 2,
-};
-
-enum a2xx_pa_pixcenter {
-       PIXCENTER_D3D = 0,
-       PIXCENTER_OGL = 1,
-};
-
-enum a2xx_pa_roundmode {
-       TRUNCATE = 0,
-       ROUND = 1,
-       ROUNDTOEVEN = 2,
-       ROUNDTOODD = 3,
-};
-
-enum a2xx_pa_quantmode {
-       ONE_SIXTEENTH = 0,
-       ONE_EIGTH = 1,
-       ONE_QUARTER = 2,
-       ONE_HALF = 3,
-       ONE = 4,
-};
-
-enum a2xx_rb_copy_sample_select {
-       SAMPLE_0 = 0,
-       SAMPLE_1 = 1,
-       SAMPLE_2 = 2,
-       SAMPLE_3 = 3,
-       SAMPLE_01 = 4,
-       SAMPLE_23 = 5,
-       SAMPLE_0123 = 6,
-};
-
-enum a2xx_rb_blend_opcode {
-       BLEND2_DST_PLUS_SRC = 0,
-       BLEND2_SRC_MINUS_DST = 1,
-       BLEND2_MIN_DST_SRC = 2,
-       BLEND2_MAX_DST_SRC = 3,
-       BLEND2_DST_MINUS_SRC = 4,
-       BLEND2_DST_PLUS_SRC_BIAS = 5,
-};
-
-enum a2xx_su_perfcnt_select {
-       PERF_PAPC_PASX_REQ = 0,
-       PERF_PAPC_PASX_FIRST_VECTOR = 2,
-       PERF_PAPC_PASX_SECOND_VECTOR = 3,
-       PERF_PAPC_PASX_FIRST_DEAD = 4,
-       PERF_PAPC_PASX_SECOND_DEAD = 5,
-       PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
-       PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
-       PERF_PAPC_PA_INPUT_PRIM = 8,
-       PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
-       PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
-       PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
-       PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
-       PERF_PAPC_CLPR_CULL_PRIM = 13,
-       PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
-       PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
-       PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
-       PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
-       PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
-       PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
-       PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
-       PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
-       PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
-       PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
-       PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
-       PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
-       PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
-       PERF_PAPC_CLSM_NULL_PRIM = 36,
-       PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
-       PERF_PAPC_CLSM_CLIP_PRIM = 38,
-       PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
-       PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
-       PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
-       PERF_PAPC_SU_INPUT_PRIM = 47,
-       PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
-       PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
-       PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
-       PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
-       PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
-       PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
-       PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
-       PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
-       PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
-       PERF_PAPC_SU_OUTPUT_PRIM = 57,
-       PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
-       PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
-       PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
-       PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
-       PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
-       PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
-       PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
-       PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
-       PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
-       PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
-       PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
-       PERF_PAPC_PASX_REQ_IDLE = 69,
-       PERF_PAPC_PASX_REQ_BUSY = 70,
-       PERF_PAPC_PASX_REQ_STALLED = 71,
-       PERF_PAPC_PASX_REC_IDLE = 72,
-       PERF_PAPC_PASX_REC_BUSY = 73,
-       PERF_PAPC_PASX_REC_STARVED_SX = 74,
-       PERF_PAPC_PASX_REC_STALLED = 75,
-       PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
-       PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
-       PERF_PAPC_CCGSM_IDLE = 78,
-       PERF_PAPC_CCGSM_BUSY = 79,
-       PERF_PAPC_CCGSM_STALLED = 80,
-       PERF_PAPC_CLPRIM_IDLE = 81,
-       PERF_PAPC_CLPRIM_BUSY = 82,
-       PERF_PAPC_CLPRIM_STALLED = 83,
-       PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
-       PERF_PAPC_CLIPSM_IDLE = 85,
-       PERF_PAPC_CLIPSM_BUSY = 86,
-       PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
-       PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
-       PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
-       PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
-       PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
-       PERF_PAPC_CLIPGA_IDLE = 92,
-       PERF_PAPC_CLIPGA_BUSY = 93,
-       PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
-       PERF_PAPC_CLIPGA_STALLED = 95,
-       PERF_PAPC_CLIP_IDLE = 96,
-       PERF_PAPC_CLIP_BUSY = 97,
-       PERF_PAPC_SU_IDLE = 98,
-       PERF_PAPC_SU_BUSY = 99,
-       PERF_PAPC_SU_STARVED_CLIP = 100,
-       PERF_PAPC_SU_STALLED_SC = 101,
-       PERF_PAPC_SU_FACENESS_CULL = 102,
-};
-
-enum a2xx_sc_perfcnt_select {
-       SC_SR_WINDOW_VALID = 0,
-       SC_CW_WINDOW_VALID = 1,
-       SC_QM_WINDOW_VALID = 2,
-       SC_FW_WINDOW_VALID = 3,
-       SC_EZ_WINDOW_VALID = 4,
-       SC_IT_WINDOW_VALID = 5,
-       SC_STARVED_BY_PA = 6,
-       SC_STALLED_BY_RB_TILE = 7,
-       SC_STALLED_BY_RB_SAMP = 8,
-       SC_STARVED_BY_RB_EZ = 9,
-       SC_STALLED_BY_SAMPLE_FF = 10,
-       SC_STALLED_BY_SQ = 11,
-       SC_STALLED_BY_SP = 12,
-       SC_TOTAL_NO_PRIMS = 13,
-       SC_NON_EMPTY_PRIMS = 14,
-       SC_NO_TILES_PASSING_QM = 15,
-       SC_NO_PIXELS_PRE_EZ = 16,
-       SC_NO_PIXELS_POST_EZ = 17,
-};
-
-enum a2xx_vgt_perfcount_select {
-       VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
-       VGT_SQ_SEND = 1,
-       VGT_SQ_STALLED = 2,
-       VGT_SQ_STARVED_BUSY = 3,
-       VGT_SQ_STARVED_IDLE = 4,
-       VGT_SQ_STATIC = 5,
-       VGT_PA_EVENT_WINDOW_ACTIVE = 6,
-       VGT_PA_CLIP_V_SEND = 7,
-       VGT_PA_CLIP_V_STALLED = 8,
-       VGT_PA_CLIP_V_STARVED_BUSY = 9,
-       VGT_PA_CLIP_V_STARVED_IDLE = 10,
-       VGT_PA_CLIP_V_STATIC = 11,
-       VGT_PA_CLIP_P_SEND = 12,
-       VGT_PA_CLIP_P_STALLED = 13,
-       VGT_PA_CLIP_P_STARVED_BUSY = 14,
-       VGT_PA_CLIP_P_STARVED_IDLE = 15,
-       VGT_PA_CLIP_P_STATIC = 16,
-       VGT_PA_CLIP_S_SEND = 17,
-       VGT_PA_CLIP_S_STALLED = 18,
-       VGT_PA_CLIP_S_STARVED_BUSY = 19,
-       VGT_PA_CLIP_S_STARVED_IDLE = 20,
-       VGT_PA_CLIP_S_STATIC = 21,
-       RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
-       RBIU_IMMED_DATA_FIFO_STARVED = 23,
-       RBIU_IMMED_DATA_FIFO_STALLED = 24,
-       RBIU_DMA_REQUEST_FIFO_STARVED = 25,
-       RBIU_DMA_REQUEST_FIFO_STALLED = 26,
-       RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
-       RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
-       BIN_PRIM_NEAR_CULL = 29,
-       BIN_PRIM_ZERO_CULL = 30,
-       BIN_PRIM_FAR_CULL = 31,
-       BIN_PRIM_BIN_CULL = 32,
-       BIN_PRIM_FACE_CULL = 33,
-       SPARE34 = 34,
-       SPARE35 = 35,
-       SPARE36 = 36,
-       SPARE37 = 37,
-       SPARE38 = 38,
-       SPARE39 = 39,
-       TE_SU_IN_VALID = 40,
-       TE_SU_IN_READ = 41,
-       TE_SU_IN_PRIM = 42,
-       TE_SU_IN_EOP = 43,
-       TE_SU_IN_NULL_PRIM = 44,
-       TE_WK_IN_VALID = 45,
-       TE_WK_IN_READ = 46,
-       TE_OUT_PRIM_VALID = 47,
-       TE_OUT_PRIM_READ = 48,
-};
-
-enum a2xx_tcr_perfcount_select {
-       DGMMPD_IPMUX0_STALL = 0,
-       DGMMPD_IPMUX_ALL_STALL = 4,
-       OPMUX0_L2_WRITES = 5,
-};
-
-enum a2xx_tp_perfcount_select {
-       POINT_QUADS = 0,
-       BILIN_QUADS = 1,
-       ANISO_QUADS = 2,
-       MIP_QUADS = 3,
-       VOL_QUADS = 4,
-       MIP_VOL_QUADS = 5,
-       MIP_ANISO_QUADS = 6,
-       VOL_ANISO_QUADS = 7,
-       ANISO_2_1_QUADS = 8,
-       ANISO_4_1_QUADS = 9,
-       ANISO_6_1_QUADS = 10,
-       ANISO_8_1_QUADS = 11,
-       ANISO_10_1_QUADS = 12,
-       ANISO_12_1_QUADS = 13,
-       ANISO_14_1_QUADS = 14,
-       ANISO_16_1_QUADS = 15,
-       MIP_VOL_ANISO_QUADS = 16,
-       ALIGN_2_QUADS = 17,
-       ALIGN_4_QUADS = 18,
-       PIX_0_QUAD = 19,
-       PIX_1_QUAD = 20,
-       PIX_2_QUAD = 21,
-       PIX_3_QUAD = 22,
-       PIX_4_QUAD = 23,
-       TP_MIPMAP_LOD0 = 24,
-       TP_MIPMAP_LOD1 = 25,
-       TP_MIPMAP_LOD2 = 26,
-       TP_MIPMAP_LOD3 = 27,
-       TP_MIPMAP_LOD4 = 28,
-       TP_MIPMAP_LOD5 = 29,
-       TP_MIPMAP_LOD6 = 30,
-       TP_MIPMAP_LOD7 = 31,
-       TP_MIPMAP_LOD8 = 32,
-       TP_MIPMAP_LOD9 = 33,
-       TP_MIPMAP_LOD10 = 34,
-       TP_MIPMAP_LOD11 = 35,
-       TP_MIPMAP_LOD12 = 36,
-       TP_MIPMAP_LOD13 = 37,
-       TP_MIPMAP_LOD14 = 38,
-};
-
-enum a2xx_tcm_perfcount_select {
-       QUAD0_RD_LAT_FIFO_EMPTY = 0,
-       QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
-       QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
-       QUAD0_RD_LAT_FIFO_FULL = 5,
-       QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
-       READ_STARVED_QUAD0 = 28,
-       READ_STARVED = 32,
-       READ_STALLED_QUAD0 = 33,
-       READ_STALLED = 37,
-       VALID_READ_QUAD0 = 38,
-       TC_TP_STARVED_QUAD0 = 42,
-       TC_TP_STARVED = 46,
-};
-
-enum a2xx_tcf_perfcount_select {
-       VALID_CYCLES = 0,
-       SINGLE_PHASES = 1,
-       ANISO_PHASES = 2,
-       MIP_PHASES = 3,
-       VOL_PHASES = 4,
-       MIP_VOL_PHASES = 5,
-       MIP_ANISO_PHASES = 6,
-       VOL_ANISO_PHASES = 7,
-       ANISO_2_1_PHASES = 8,
-       ANISO_4_1_PHASES = 9,
-       ANISO_6_1_PHASES = 10,
-       ANISO_8_1_PHASES = 11,
-       ANISO_10_1_PHASES = 12,
-       ANISO_12_1_PHASES = 13,
-       ANISO_14_1_PHASES = 14,
-       ANISO_16_1_PHASES = 15,
-       MIP_VOL_ANISO_PHASES = 16,
-       ALIGN_2_PHASES = 17,
-       ALIGN_4_PHASES = 18,
-       TPC_BUSY = 19,
-       TPC_STALLED = 20,
-       TPC_STARVED = 21,
-       TPC_WORKING = 22,
-       TPC_WALKER_BUSY = 23,
-       TPC_WALKER_STALLED = 24,
-       TPC_WALKER_WORKING = 25,
-       TPC_ALIGNER_BUSY = 26,
-       TPC_ALIGNER_STALLED = 27,
-       TPC_ALIGNER_STALLED_BY_BLEND = 28,
-       TPC_ALIGNER_STALLED_BY_CACHE = 29,
-       TPC_ALIGNER_WORKING = 30,
-       TPC_BLEND_BUSY = 31,
-       TPC_BLEND_SYNC = 32,
-       TPC_BLEND_STARVED = 33,
-       TPC_BLEND_WORKING = 34,
-       OPCODE_0x00 = 35,
-       OPCODE_0x01 = 36,
-       OPCODE_0x04 = 37,
-       OPCODE_0x10 = 38,
-       OPCODE_0x11 = 39,
-       OPCODE_0x12 = 40,
-       OPCODE_0x13 = 41,
-       OPCODE_0x18 = 42,
-       OPCODE_0x19 = 43,
-       OPCODE_0x1A = 44,
-       OPCODE_OTHER = 45,
-       IN_FIFO_0_EMPTY = 56,
-       IN_FIFO_0_LT_HALF_FULL = 57,
-       IN_FIFO_0_HALF_FULL = 58,
-       IN_FIFO_0_FULL = 59,
-       IN_FIFO_TPC_EMPTY = 72,
-       IN_FIFO_TPC_LT_HALF_FULL = 73,
-       IN_FIFO_TPC_HALF_FULL = 74,
-       IN_FIFO_TPC_FULL = 75,
-       TPC_TC_XFC = 76,
-       TPC_TC_STATE = 77,
-       TC_STALL = 78,
-       QUAD0_TAPS = 79,
-       QUADS = 83,
-       TCA_SYNC_STALL = 84,
-       TAG_STALL = 85,
-       TCB_SYNC_STALL = 88,
-       TCA_VALID = 89,
-       PROBES_VALID = 90,
-       MISS_STALL = 91,
-       FETCH_FIFO_STALL = 92,
-       TCO_STALL = 93,
-       ANY_STALL = 94,
-       TAG_MISSES = 95,
-       TAG_HITS = 96,
-       SUB_TAG_MISSES = 97,
-       SET0_INVALIDATES = 98,
-       SET1_INVALIDATES = 99,
-       SET2_INVALIDATES = 100,
-       SET3_INVALIDATES = 101,
-       SET0_TAG_MISSES = 102,
-       SET1_TAG_MISSES = 103,
-       SET2_TAG_MISSES = 104,
-       SET3_TAG_MISSES = 105,
-       SET0_TAG_HITS = 106,
-       SET1_TAG_HITS = 107,
-       SET2_TAG_HITS = 108,
-       SET3_TAG_HITS = 109,
-       SET0_SUB_TAG_MISSES = 110,
-       SET1_SUB_TAG_MISSES = 111,
-       SET2_SUB_TAG_MISSES = 112,
-       SET3_SUB_TAG_MISSES = 113,
-       SET0_EVICT1 = 114,
-       SET0_EVICT2 = 115,
-       SET0_EVICT3 = 116,
-       SET0_EVICT4 = 117,
-       SET0_EVICT5 = 118,
-       SET0_EVICT6 = 119,
-       SET0_EVICT7 = 120,
-       SET0_EVICT8 = 121,
-       SET1_EVICT1 = 130,
-       SET1_EVICT2 = 131,
-       SET1_EVICT3 = 132,
-       SET1_EVICT4 = 133,
-       SET1_EVICT5 = 134,
-       SET1_EVICT6 = 135,
-       SET1_EVICT7 = 136,
-       SET1_EVICT8 = 137,
-       SET2_EVICT1 = 146,
-       SET2_EVICT2 = 147,
-       SET2_EVICT3 = 148,
-       SET2_EVICT4 = 149,
-       SET2_EVICT5 = 150,
-       SET2_EVICT6 = 151,
-       SET2_EVICT7 = 152,
-       SET2_EVICT8 = 153,
-       SET3_EVICT1 = 162,
-       SET3_EVICT2 = 163,
-       SET3_EVICT3 = 164,
-       SET3_EVICT4 = 165,
-       SET3_EVICT5 = 166,
-       SET3_EVICT6 = 167,
-       SET3_EVICT7 = 168,
-       SET3_EVICT8 = 169,
-       FF_EMPTY = 178,
-       FF_LT_HALF_FULL = 179,
-       FF_HALF_FULL = 180,
-       FF_FULL = 181,
-       FF_XFC = 182,
-       FF_STALLED = 183,
-       FG_MASKS = 184,
-       FG_LEFT_MASKS = 185,
-       FG_LEFT_MASK_STALLED = 186,
-       FG_LEFT_NOT_DONE_STALL = 187,
-       FG_LEFT_FG_STALL = 188,
-       FG_LEFT_SECTORS = 189,
-       FG0_REQUESTS = 195,
-       FG0_STALLED = 196,
-       MEM_REQ512 = 199,
-       MEM_REQ_SENT = 200,
-       MEM_LOCAL_READ_REQ = 202,
-       TC0_MH_STALLED = 203,
-};
-
-enum a2xx_sq_perfcnt_select {
-       SQ_PIXEL_VECTORS_SUB = 0,
-       SQ_VERTEX_VECTORS_SUB = 1,
-       SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
-       SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
-       SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
-       SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
-       SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
-       SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
-       SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
-       SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
-       SQ_EXPORT_CYCLES = 10,
-       SQ_ALU_CST_WRITTEN = 11,
-       SQ_TEX_CST_WRITTEN = 12,
-       SQ_ALU_CST_STALL = 13,
-       SQ_ALU_TEX_STALL = 14,
-       SQ_INST_WRITTEN = 15,
-       SQ_BOOLEAN_WRITTEN = 16,
-       SQ_LOOPS_WRITTEN = 17,
-       SQ_PIXEL_SWAP_IN = 18,
-       SQ_PIXEL_SWAP_OUT = 19,
-       SQ_VERTEX_SWAP_IN = 20,
-       SQ_VERTEX_SWAP_OUT = 21,
-       SQ_ALU_VTX_INST_ISSUED = 22,
-       SQ_TEX_VTX_INST_ISSUED = 23,
-       SQ_VC_VTX_INST_ISSUED = 24,
-       SQ_CF_VTX_INST_ISSUED = 25,
-       SQ_ALU_PIX_INST_ISSUED = 26,
-       SQ_TEX_PIX_INST_ISSUED = 27,
-       SQ_VC_PIX_INST_ISSUED = 28,
-       SQ_CF_PIX_INST_ISSUED = 29,
-       SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
-       SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
-       SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
-       SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
-       SQ_ALU_NOPS = 34,
-       SQ_PRED_SKIP = 35,
-       SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
-       SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
-       SQ_SYNC_TEX_STALL_VTX = 38,
-       SQ_SYNC_VC_STALL_VTX = 39,
-       SQ_CONSTANTS_USED_SIMD0 = 40,
-       SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
-       SQ_GPR_STALL_VTX = 42,
-       SQ_GPR_STALL_PIX = 43,
-       SQ_VTX_RS_STALL = 44,
-       SQ_PIX_RS_STALL = 45,
-       SQ_SX_PC_FULL = 46,
-       SQ_SX_EXP_BUFF_FULL = 47,
-       SQ_SX_POS_BUFF_FULL = 48,
-       SQ_INTERP_QUADS = 49,
-       SQ_INTERP_ACTIVE = 50,
-       SQ_IN_PIXEL_STALL = 51,
-       SQ_IN_VTX_STALL = 52,
-       SQ_VTX_CNT = 53,
-       SQ_VTX_VECTOR2 = 54,
-       SQ_VTX_VECTOR3 = 55,
-       SQ_VTX_VECTOR4 = 56,
-       SQ_PIXEL_VECTOR1 = 57,
-       SQ_PIXEL_VECTOR23 = 58,
-       SQ_PIXEL_VECTOR4 = 59,
-       SQ_CONSTANTS_USED_SIMD1 = 60,
-       SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
-       SQ_SX_MEM_EXP_FULL = 62,
-       SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
-       SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
-       SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
-       SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
-       SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
-       SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
-       SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
-       SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
-       SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
-       SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
-       SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
-       SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
-       SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
-       SQ_PERFCOUNT_VTX_POP_THREAD = 76,
-       SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
-       SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
-       SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
-       SQ_PERFCOUNT_PIX_POP_THREAD = 80,
-       SQ_SYNC_TEX_STALL_PIX = 81,
-       SQ_SYNC_VC_STALL_PIX = 82,
-       SQ_CONSTANTS_USED_SIMD2 = 83,
-       SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
-       SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
-       SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
-       SQ_ALU0_FIFO_FULL_SIMD0 = 87,
-       SQ_ALU1_FIFO_FULL_SIMD0 = 88,
-       SQ_ALU0_FIFO_FULL_SIMD1 = 89,
-       SQ_ALU1_FIFO_FULL_SIMD1 = 90,
-       SQ_ALU0_FIFO_FULL_SIMD2 = 91,
-       SQ_ALU1_FIFO_FULL_SIMD2 = 92,
-       SQ_ALU0_FIFO_FULL_SIMD3 = 93,
-       SQ_ALU1_FIFO_FULL_SIMD3 = 94,
-       VC_PERF_STATIC = 95,
-       VC_PERF_STALLED = 96,
-       VC_PERF_STARVED = 97,
-       VC_PERF_SEND = 98,
-       VC_PERF_ACTUAL_STARVED = 99,
-       PIXEL_THREAD_0_ACTIVE = 100,
-       VERTEX_THREAD_0_ACTIVE = 101,
-       PIXEL_THREAD_0_NUMBER = 102,
-       VERTEX_THREAD_0_NUMBER = 103,
-       VERTEX_EVENT_NUMBER = 104,
-       PIXEL_EVENT_NUMBER = 105,
-       PTRBUFF_EF_PUSH = 106,
-       PTRBUFF_EF_POP_EVENT = 107,
-       PTRBUFF_EF_POP_NEW_VTX = 108,
-       PTRBUFF_EF_POP_DEALLOC = 109,
-       PTRBUFF_EF_POP_PVECTOR = 110,
-       PTRBUFF_EF_POP_PVECTOR_X = 111,
-       PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
-       PTRBUFF_PB_DEALLOC = 113,
-       PTRBUFF_PI_STATE_PPB_POP = 114,
-       PTRBUFF_PI_RTR = 115,
-       PTRBUFF_PI_READ_EN = 116,
-       PTRBUFF_PI_BUFF_SWAP = 117,
-       PTRBUFF_SQ_FREE_BUFF = 118,
-       PTRBUFF_SQ_DEC = 119,
-       PTRBUFF_SC_VALID_CNTL_EVENT = 120,
-       PTRBUFF_SC_VALID_IJ_XFER = 121,
-       PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
-       PTRBUFF_QUAL_NEW_VECTOR = 123,
-       PTRBUFF_QUAL_EVENT = 124,
-       PTRBUFF_END_BUFFER = 125,
-       PTRBUFF_FILL_QUAD = 126,
-       VERTS_WRITTEN_SPI = 127,
-       TP_FETCH_INSTR_EXEC = 128,
-       TP_FETCH_INSTR_REQ = 129,
-       TP_DATA_RETURN = 130,
-       SPI_WRITE_CYCLES_SP = 131,
-       SPI_WRITES_SP = 132,
-       SP_ALU_INSTR_EXEC = 133,
-       SP_CONST_ADDR_TO_SQ = 134,
-       SP_PRED_KILLS_TO_SQ = 135,
-       SP_EXPORT_CYCLES_TO_SX = 136,
-       SP_EXPORTS_TO_SX = 137,
-       SQ_CYCLES_ELAPSED = 138,
-       SQ_TCFS_OPT_ALLOC_EXEC = 139,
-       SQ_TCFS_NO_OPT_ALLOC = 140,
-       SQ_ALU0_NO_OPT_ALLOC = 141,
-       SQ_ALU1_NO_OPT_ALLOC = 142,
-       SQ_TCFS_ARB_XFC_CNT = 143,
-       SQ_ALU0_ARB_XFC_CNT = 144,
-       SQ_ALU1_ARB_XFC_CNT = 145,
-       SQ_TCFS_CFS_UPDATE_CNT = 146,
-       SQ_ALU0_CFS_UPDATE_CNT = 147,
-       SQ_ALU1_CFS_UPDATE_CNT = 148,
-       SQ_VTX_PUSH_THREAD_CNT = 149,
-       SQ_VTX_POP_THREAD_CNT = 150,
-       SQ_PIX_PUSH_THREAD_CNT = 151,
-       SQ_PIX_POP_THREAD_CNT = 152,
-       SQ_PIX_TOTAL = 153,
-       SQ_PIX_KILLED = 154,
-};
-
-enum a2xx_sx_perfcnt_select {
-       SX_EXPORT_VECTORS = 0,
-       SX_DUMMY_QUADS = 1,
-       SX_ALPHA_FAIL = 2,
-       SX_RB_QUAD_BUSY = 3,
-       SX_RB_COLOR_BUSY = 4,
-       SX_RB_QUAD_STALL = 5,
-       SX_RB_COLOR_STALL = 6,
-};
-
-enum a2xx_rbbm_perfcount1_sel {
-       RBBM1_COUNT = 0,
-       RBBM1_NRT_BUSY = 1,
-       RBBM1_RB_BUSY = 2,
-       RBBM1_SQ_CNTX0_BUSY = 3,
-       RBBM1_SQ_CNTX17_BUSY = 4,
-       RBBM1_VGT_BUSY = 5,
-       RBBM1_VGT_NODMA_BUSY = 6,
-       RBBM1_PA_BUSY = 7,
-       RBBM1_SC_CNTX_BUSY = 8,
-       RBBM1_TPC_BUSY = 9,
-       RBBM1_TC_BUSY = 10,
-       RBBM1_SX_BUSY = 11,
-       RBBM1_CP_COHER_BUSY = 12,
-       RBBM1_CP_NRT_BUSY = 13,
-       RBBM1_GFX_IDLE_STALL = 14,
-       RBBM1_INTERRUPT = 15,
-};
-
-enum a2xx_cp_perfcount_sel {
-       ALWAYS_COUNT = 0,
-       TRANS_FIFO_FULL = 1,
-       TRANS_FIFO_AF = 2,
-       RCIU_PFPTRANS_WAIT = 3,
-       RCIU_NRTTRANS_WAIT = 6,
-       CSF_NRT_READ_WAIT = 8,
-       CSF_I1_FIFO_FULL = 9,
-       CSF_I2_FIFO_FULL = 10,
-       CSF_ST_FIFO_FULL = 11,
-       CSF_RING_ROQ_FULL = 13,
-       CSF_I1_ROQ_FULL = 14,
-       CSF_I2_ROQ_FULL = 15,
-       CSF_ST_ROQ_FULL = 16,
-       MIU_TAG_MEM_FULL = 18,
-       MIU_WRITECLEAN = 19,
-       MIU_NRT_WRITE_STALLED = 22,
-       MIU_NRT_READ_STALLED = 23,
-       ME_WRITE_CONFIRM_FIFO_FULL = 24,
-       ME_VS_DEALLOC_FIFO_FULL = 25,
-       ME_PS_DEALLOC_FIFO_FULL = 26,
-       ME_REGS_VS_EVENT_FIFO_FULL = 27,
-       ME_REGS_PS_EVENT_FIFO_FULL = 28,
-       ME_REGS_CF_EVENT_FIFO_FULL = 29,
-       ME_MICRO_RB_STARVED = 30,
-       ME_MICRO_I1_STARVED = 31,
-       ME_MICRO_I2_STARVED = 32,
-       ME_MICRO_ST_STARVED = 33,
-       RCIU_RBBM_DWORD_SENT = 40,
-       ME_BUSY_CLOCKS = 41,
-       ME_WAIT_CONTEXT_AVAIL = 42,
-       PFP_TYPE0_PACKET = 43,
-       PFP_TYPE3_PACKET = 44,
-       CSF_RB_WPTR_NEQ_RPTR = 45,
-       CSF_I1_SIZE_NEQ_ZERO = 46,
-       CSF_I2_SIZE_NEQ_ZERO = 47,
-       CSF_RBI1I2_FETCHING = 48,
-};
-
-enum a2xx_rb_perfcnt_select {
-       RBPERF_CNTX_BUSY = 0,
-       RBPERF_CNTX_BUSY_MAX = 1,
-       RBPERF_SX_QUAD_STARVED = 2,
-       RBPERF_SX_QUAD_STARVED_MAX = 3,
-       RBPERF_GA_GC_CH0_SYS_REQ = 4,
-       RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
-       RBPERF_GA_GC_CH1_SYS_REQ = 6,
-       RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
-       RBPERF_MH_STARVED = 8,
-       RBPERF_MH_STARVED_MAX = 9,
-       RBPERF_AZ_BC_COLOR_BUSY = 10,
-       RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
-       RBPERF_AZ_BC_Z_BUSY = 12,
-       RBPERF_AZ_BC_Z_BUSY_MAX = 13,
-       RBPERF_RB_SC_TILE_RTR_N = 14,
-       RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
-       RBPERF_RB_SC_SAMP_RTR_N = 16,
-       RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
-       RBPERF_RB_SX_QUAD_RTR_N = 18,
-       RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
-       RBPERF_RB_SX_COLOR_RTR_N = 20,
-       RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
-       RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
-       RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
-       RBPERF_ZXP_STALL = 24,
-       RBPERF_ZXP_STALL_MAX = 25,
-       RBPERF_EVENT_PENDING = 26,
-       RBPERF_EVENT_PENDING_MAX = 27,
-       RBPERF_RB_MH_VALID = 28,
-       RBPERF_RB_MH_VALID_MAX = 29,
-       RBPERF_SX_RB_QUAD_SEND = 30,
-       RBPERF_SX_RB_COLOR_SEND = 31,
-       RBPERF_SC_RB_TILE_SEND = 32,
-       RBPERF_SC_RB_SAMPLE_SEND = 33,
-       RBPERF_SX_RB_MEM_EXPORT = 34,
-       RBPERF_SX_RB_QUAD_EVENT = 35,
-       RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
-       RBPERF_SC_RB_TILE_EVENT_ALL = 37,
-       RBPERF_RB_SC_EZ_SEND = 38,
-       RBPERF_RB_SX_INDEX_SEND = 39,
-       RBPERF_GMEM_INTFO_RD = 40,
-       RBPERF_GMEM_INTF1_RD = 41,
-       RBPERF_GMEM_INTFO_WR = 42,
-       RBPERF_GMEM_INTF1_WR = 43,
-       RBPERF_RB_CP_CONTEXT_DONE = 44,
-       RBPERF_RB_CP_CACHE_FLUSH = 45,
-       RBPERF_ZPASS_DONE = 46,
-       RBPERF_ZCMD_VALID = 47,
-       RBPERF_CCMD_VALID = 48,
-       RBPERF_ACCUM_GRANT = 49,
-       RBPERF_ACCUM_C0_GRANT = 50,
-       RBPERF_ACCUM_C1_GRANT = 51,
-       RBPERF_ACCUM_FULL_BE_WR = 52,
-       RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
-       RBPERF_ACCUM_TIMEOUT_PULSE = 54,
-       RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
-       RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
-};
-
-enum adreno_mmu_clnt_beh {
-       BEH_NEVR = 0,
-       BEH_TRAN_RNG = 1,
-       BEH_TRAN_FLT = 2,
-};
-
-enum sq_tex_clamp {
-       SQ_TEX_WRAP = 0,
-       SQ_TEX_MIRROR = 1,
-       SQ_TEX_CLAMP_LAST_TEXEL = 2,
-       SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
-       SQ_TEX_CLAMP_HALF_BORDER = 4,
-       SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
-       SQ_TEX_CLAMP_BORDER = 6,
-       SQ_TEX_MIRROR_ONCE_BORDER = 7,
-};
-
-enum sq_tex_swiz {
-       SQ_TEX_X = 0,
-       SQ_TEX_Y = 1,
-       SQ_TEX_Z = 2,
-       SQ_TEX_W = 3,
-       SQ_TEX_ZERO = 4,
-       SQ_TEX_ONE = 5,
-};
-
-enum sq_tex_filter {
-       SQ_TEX_FILTER_POINT = 0,
-       SQ_TEX_FILTER_BILINEAR = 1,
-       SQ_TEX_FILTER_BASEMAP = 2,
-       SQ_TEX_FILTER_USE_FETCH_CONST = 3,
-};
-
-enum sq_tex_aniso_filter {
-       SQ_TEX_ANISO_FILTER_DISABLED = 0,
-       SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
-       SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
-       SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
-       SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
-       SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
-       SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
-};
-
-enum sq_tex_dimension {
-       SQ_TEX_DIMENSION_1D = 0,
-       SQ_TEX_DIMENSION_2D = 1,
-       SQ_TEX_DIMENSION_3D = 2,
-       SQ_TEX_DIMENSION_CUBE = 3,
-};
-
-enum sq_tex_border_color {
-       SQ_TEX_BORDER_COLOR_BLACK = 0,
-       SQ_TEX_BORDER_COLOR_WHITE = 1,
-       SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
-       SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
-};
-
-enum sq_tex_sign {
-       SQ_TEX_SIGN_UNISIGNED = 0,
-       SQ_TEX_SIGN_SIGNED = 1,
-       SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
-       SQ_TEX_SIGN_GAMMA = 3,
-};
-
-enum sq_tex_endian {
-       SQ_TEX_ENDIAN_NONE = 0,
-       SQ_TEX_ENDIAN_8IN16 = 1,
-       SQ_TEX_ENDIAN_8IN32 = 2,
-       SQ_TEX_ENDIAN_16IN32 = 3,
-};
-
-enum sq_tex_clamp_policy {
-       SQ_TEX_CLAMP_POLICY_D3D = 0,
-       SQ_TEX_CLAMP_POLICY_OGL = 1,
-};
-
-enum sq_tex_num_format {
-       SQ_TEX_NUM_FORMAT_FRAC = 0,
-       SQ_TEX_NUM_FORMAT_INT = 1,
-};
-
-enum sq_tex_type {
-       SQ_TEX_TYPE_0 = 0,
-       SQ_TEX_TYPE_1 = 1,
-       SQ_TEX_TYPE_2 = 2,
-       SQ_TEX_TYPE_3 = 3,
-};
-
-#define REG_A2XX_RBBM_PATCH_RELEASE                            0x00000001
-
-#define REG_A2XX_RBBM_CNTL                                     0x0000003b
-
-#define REG_A2XX_RBBM_SOFT_RESET                               0x0000003c
-
-#define REG_A2XX_CP_PFP_UCODE_ADDR                             0x000000c0
-
-#define REG_A2XX_CP_PFP_UCODE_DATA                             0x000000c1
-
-#define REG_A2XX_MH_MMU_CONFIG                                 0x00000040
-#define A2XX_MH_MMU_CONFIG_MMU_ENABLE                          0x00000001
-#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                   0x00000002
-#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK            0x00000030
-#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT           4
-static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK            0x000000c0
-#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT           6
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK           0x00000300
-#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT          8
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK           0x00000c00
-#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT          10
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK           0x00003000
-#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT          12
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK           0x0000c000
-#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT          14
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK           0x00030000
-#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT          16
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK          0x000c0000
-#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT         18
-static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK          0x00300000
-#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT         20
-static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK            0x00c00000
-#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT           22
-static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK            0x03000000
-#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT           24
-static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
-       return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
-}
-
-#define REG_A2XX_MH_MMU_VA_RANGE                               0x00000041
-#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK            0x00000fff
-#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT           0
-static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
-{
-       return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
-}
-#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK                     0xfffff000
-#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT                    12
-static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
-{
-       return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
-}
-
-#define REG_A2XX_MH_MMU_PT_BASE                                        0x00000042
-
-#define REG_A2XX_MH_MMU_PAGE_FAULT                             0x00000043
-
-#define REG_A2XX_MH_MMU_TRAN_ERROR                             0x00000044
-
-#define REG_A2XX_MH_MMU_INVALIDATE                             0x00000045
-#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL                  0x00000001
-#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC                   0x00000002
-
-#define REG_A2XX_MH_MMU_MPU_BASE                               0x00000046
-
-#define REG_A2XX_MH_MMU_MPU_END                                        0x00000047
-
-#define REG_A2XX_NQWAIT_UNTIL                                  0x00000394
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                      0x00000395
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_LO                          0x00000397
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_HI                          0x00000398
-
-#define REG_A2XX_RBBM_DEBUG                                    0x0000039b
-
-#define REG_A2XX_RBBM_PM_OVERRIDE1                             0x0000039c
-#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE         0x00000001
-#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE         0x00000002
-#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE             0x00000004
-#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE         0x00000008
-#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE          0x00000010
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE         0x00000020
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE   0x00000040
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE   0x00000080
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE          0x00000100
-#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE             0x00000200
-#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE         0x00000400
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE                0x00000800
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE                0x00001000
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE                0x00002000
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE                0x00004000
-#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE                0x00008000
-#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE                0x00010000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE                0x00020000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE                0x00040000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE   0x00080000
-#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE          0x00100000
-#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE         0x00200000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE           0x00400000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE         0x00800000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE       0x01000000
-#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE            0x02000000
-#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE         0x04000000
-#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE             0x08000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE          0x10000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE         0x20000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE         0x40000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE       0x80000000
-
-#define REG_A2XX_RBBM_PM_OVERRIDE2                             0x0000039d
-
-#define REG_A2XX_RBBM_DEBUG_OUT                                        0x000003a0
-
-#define REG_A2XX_RBBM_DEBUG_CNTL                               0x000003a1
-
-#define REG_A2XX_RBBM_READ_ERROR                               0x000003b3
-
-#define REG_A2XX_RBBM_INT_CNTL                                 0x000003b4
-#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK                      0x00000001
-#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK             0x00000002
-#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK                   0x00080000
-
-#define REG_A2XX_RBBM_INT_STATUS                               0x000003b5
-
-#define REG_A2XX_RBBM_INT_ACK                                  0x000003b6
-
-#define REG_A2XX_MASTER_INT_SIGNAL                             0x000003b7
-#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT                     0x00000020
-#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT                     0x04000000
-#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT                     0x40000000
-#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT                   0x80000000
-
-#define REG_A2XX_RBBM_PERIPHID1                                        0x000003f9
-
-#define REG_A2XX_RBBM_PERIPHID2                                        0x000003fa
-
-#define REG_A2XX_CP_PERFMON_CNTL                               0x00000444
-
-#define REG_A2XX_CP_PERFCOUNTER_SELECT                         0x00000445
-
-#define REG_A2XX_CP_PERFCOUNTER_LO                             0x00000446
-
-#define REG_A2XX_CP_PERFCOUNTER_HI                             0x00000447
-
-#define REG_A2XX_RBBM_STATUS                                   0x000005d0
-#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK                   0x0000001f
-#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT                  0
-static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
-{
-       return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
-}
-#define A2XX_RBBM_STATUS_TC_BUSY                               0x00000020
-#define A2XX_RBBM_STATUS_HIRQ_PENDING                          0x00000100
-#define A2XX_RBBM_STATUS_CPRQ_PENDING                          0x00000200
-#define A2XX_RBBM_STATUS_CFRQ_PENDING                          0x00000400
-#define A2XX_RBBM_STATUS_PFRQ_PENDING                          0x00000800
-#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA                       0x00001000
-#define A2XX_RBBM_STATUS_RBBM_WU_BUSY                          0x00004000
-#define A2XX_RBBM_STATUS_CP_NRT_BUSY                           0x00010000
-#define A2XX_RBBM_STATUS_MH_BUSY                               0x00040000
-#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY                     0x00080000
-#define A2XX_RBBM_STATUS_SX_BUSY                               0x00200000
-#define A2XX_RBBM_STATUS_TPC_BUSY                              0x00400000
-#define A2XX_RBBM_STATUS_SC_CNTX_BUSY                          0x01000000
-#define A2XX_RBBM_STATUS_PA_BUSY                               0x02000000
-#define A2XX_RBBM_STATUS_VGT_BUSY                              0x04000000
-#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY                                0x08000000
-#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY                         0x10000000
-#define A2XX_RBBM_STATUS_RB_CNTX_BUSY                          0x40000000
-#define A2XX_RBBM_STATUS_GUI_ACTIVE                            0x80000000
-
-#define REG_A2XX_MH_ARBITER_CONFIG                             0x00000a40
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK           0x0000003f
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT          0
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
-{
-       return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY           0x00000040
-#define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE                   0x00000080
-#define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE              0x00000100
-#define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL                  0x00000200
-#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK                 0x00001c00
-#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT                        10
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE               0x00002000
-#define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE              0x00004000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE          0x00008000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK           0x003f0000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT          16
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
-{
-       return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE                  0x00400000
-#define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE                 0x00800000
-#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE                  0x01000000
-#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE                  0x02000000
-#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE                  0x04000000
-
-#define REG_A2XX_MH_INTERRUPT_MASK                             0x00000a42
-#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR                  0x00000001
-#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR                 0x00000002
-#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT                  0x00000004
-
-#define REG_A2XX_MH_INTERRUPT_STATUS                           0x00000a43
-
-#define REG_A2XX_MH_INTERRUPT_CLEAR                            0x00000a44
-
-#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1                     0x00000a54
-
-#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2                     0x00000a55
-
-#define REG_A2XX_A220_VSC_BIN_SIZE                             0x00000c01
-#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK                     0x0000001f
-#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT                    0
-static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
-       assert(!(val & 0x1f));
-       return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK                    0x000003e0
-#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT                   5
-static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
-       assert(!(val & 0x1f));
-       return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
-
-static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
-
-static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
-
-static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
-
-#define REG_A2XX_PC_DEBUG_CNTL                                 0x00000c38
-
-#define REG_A2XX_PC_DEBUG_DATA                                 0x00000c39
-
-#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS                                0x00000c44
-
-#define REG_A2XX_GRAS_DEBUG_CNTL                               0x00000c80
-
-#define REG_A2XX_PA_SU_DEBUG_CNTL                              0x00000c80
-
-#define REG_A2XX_GRAS_DEBUG_DATA                               0x00000c81
-
-#define REG_A2XX_PA_SU_DEBUG_DATA                              0x00000c81
-
-#define REG_A2XX_PA_SU_FACE_DATA                               0x00000c86
-#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK                   0xffffffe0
-#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT                  5
-static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
-{
-       return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
-}
-
-#define REG_A2XX_SQ_GPR_MANAGEMENT                             0x00000d00
-#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC                     0x00000001
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK              0x00000ff0
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT             4
-static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
-{
-       return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
-}
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK              0x000ff000
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT             12
-static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
-{
-       return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
-}
-
-#define REG_A2XX_SQ_FLOW_CONTROL                               0x00000d01
-
-#define REG_A2XX_SQ_INST_STORE_MANAGMENT                       0x00000d02
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK       0x00000fff
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT      0
-static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
-{
-       return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
-}
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK       0x0fff0000
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT      16
-static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
-{
-       return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
-}
-
-#define REG_A2XX_SQ_DEBUG_MISC                                 0x00000d05
-
-#define REG_A2XX_SQ_INT_CNTL                                   0x00000d34
-
-#define REG_A2XX_SQ_INT_STATUS                                 0x00000d35
-
-#define REG_A2XX_SQ_INT_ACK                                    0x00000d36
-
-#define REG_A2XX_SQ_DEBUG_INPUT_FSM                            0x00000dae
-
-#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM                                0x00000daf
-
-#define REG_A2XX_SQ_DEBUG_TP_FSM                               0x00000db0
-
-#define REG_A2XX_SQ_DEBUG_FSM_ALU_0                            0x00000db1
-
-#define REG_A2XX_SQ_DEBUG_FSM_ALU_1                            0x00000db2
-
-#define REG_A2XX_SQ_DEBUG_EXP_ALLOC                            0x00000db3
-
-#define REG_A2XX_SQ_DEBUG_PTR_BUFF                             0x00000db4
-
-#define REG_A2XX_SQ_DEBUG_GPR_VTX                              0x00000db5
-
-#define REG_A2XX_SQ_DEBUG_GPR_PIX                              0x00000db6
-
-#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL                                0x00000db7
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_0                             0x00000db8
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_1                             0x00000db9
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG                    0x00000dba
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM                     0x00000dbb
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_0                             0x00000dbc
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0                  0x00000dbd
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1                  0x00000dbe
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2                  0x00000dbf
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3                  0x00000dc0
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM                     0x00000dc1
-
-#define REG_A2XX_TC_CNTL_STATUS                                        0x00000e00
-#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE                      0x00000001
-
-#define REG_A2XX_TP0_CHICKEN                                   0x00000e1e
-
-#define REG_A2XX_RB_BC_CONTROL                                 0x00000f01
-#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE            0x00000001
-#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK          0x00000006
-#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT         1
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
-{
-       return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM                   0x00000008
-#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH      0x00000010
-#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP           0x00000020
-#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP           0x00000040
-#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE                  0x00000080
-#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK             0x00001f00
-#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT            8
-static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
-{
-       return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE                   0x00004000
-#define A2XX_RB_BC_CONTROL_CRC_MODE                            0x00008000
-#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS             0x00010000
-#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM                       0x00020000
-#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK              0x003c0000
-#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT             18
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
-}
-#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE           0x00400000
-#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK         0x07800000
-#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT                23
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
-{
-       return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK     0x18000000
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT    27
-static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
-{
-       return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE       0x20000000
-#define A2XX_RB_BC_CONTROL_CRC_SYSTEM                          0x40000000
-#define A2XX_RB_BC_CONTROL_RESERVED6                           0x80000000
-
-#define REG_A2XX_RB_EDRAM_INFO                                 0x00000f02
-
-#define REG_A2XX_RB_DEBUG_CNTL                                 0x00000f26
-
-#define REG_A2XX_RB_DEBUG_DATA                                 0x00000f27
-
-#define REG_A2XX_RB_SURFACE_INFO                               0x00002000
-#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK               0x00003fff
-#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT              0
-static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
-{
-       return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
-}
-#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK                        0x0000c000
-#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT               14
-static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
-{
-       return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
-}
-
-#define REG_A2XX_RB_COLOR_INFO                                 0x00002001
-#define A2XX_RB_COLOR_INFO_FORMAT__MASK                                0x0000000f
-#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT                       0
-static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
-{
-       return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
-}
-#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK                    0x00000030
-#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT                   4
-static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
-}
-#define A2XX_RB_COLOR_INFO_LINEAR                              0x00000040
-#define A2XX_RB_COLOR_INFO_ENDIAN__MASK                                0x00000180
-#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT                       7
-static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
-}
-#define A2XX_RB_COLOR_INFO_SWAP__MASK                          0x00000600
-#define A2XX_RB_COLOR_INFO_SWAP__SHIFT                         9
-static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
-}
-#define A2XX_RB_COLOR_INFO_BASE__MASK                          0xfffff000
-#define A2XX_RB_COLOR_INFO_BASE__SHIFT                         12
-static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
-{
-       assert(!(val & 0xfff));
-       return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
-}
-
-#define REG_A2XX_RB_DEPTH_INFO                                 0x00002002
-#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                  0x00000001
-#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                 0
-static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
-{
-       return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
-}
-#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                    0xfffff000
-#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                   12
-static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
-{
-       assert(!(val & 0xfff));
-       return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
-}
-
-#define REG_A2XX_A225_RB_COLOR_INFO3                           0x00002005
-
-#define REG_A2XX_COHER_DEST_BASE_0                             0x00002006
-
-#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL                       0x0000200e
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE     0x80000000
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK                   0x00007fff
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT                  0
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
-}
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK                   0x7fff0000
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT                  16
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR                       0x0000200f
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE     0x80000000
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK                   0x00007fff
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT                  0
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
-}
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK                   0x7fff0000
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT                  16
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_WINDOW_OFFSET                           0x00002080
-#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK                       0x00007fff
-#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT                      0
-static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK                       0x7fff0000
-#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                      16
-static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
-}
-#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE                       0x80000000
-
-#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL                       0x00002081
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE     0x80000000
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK                   0x00007fff
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT                  0
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK                   0x7fff0000
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT                  16
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR                       0x00002082
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE     0x80000000
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK                   0x00007fff
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT                  0
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK                   0x7fff0000
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT                  16
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A2XX_UNKNOWN_2010                                  0x00002010
-
-#define REG_A2XX_VGT_MAX_VTX_INDX                              0x00002100
-
-#define REG_A2XX_VGT_MIN_VTX_INDX                              0x00002101
-
-#define REG_A2XX_VGT_INDX_OFFSET                               0x00002102
-
-#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX              0x00002103
-
-#define REG_A2XX_RB_COLOR_MASK                                 0x00002104
-#define A2XX_RB_COLOR_MASK_WRITE_RED                           0x00000001
-#define A2XX_RB_COLOR_MASK_WRITE_GREEN                         0x00000002
-#define A2XX_RB_COLOR_MASK_WRITE_BLUE                          0x00000004
-#define A2XX_RB_COLOR_MASK_WRITE_ALPHA                         0x00000008
-
-#define REG_A2XX_RB_BLEND_RED                                  0x00002105
-
-#define REG_A2XX_RB_BLEND_GREEN                                        0x00002106
-
-#define REG_A2XX_RB_BLEND_BLUE                                 0x00002107
-
-#define REG_A2XX_RB_BLEND_ALPHA                                        0x00002108
-
-#define REG_A2XX_RB_FOG_COLOR                                  0x00002109
-#define A2XX_RB_FOG_COLOR_FOG_RED__MASK                                0x000000ff
-#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT                       0
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
-{
-       return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
-}
-#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK                      0x0000ff00
-#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT                     8
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
-{
-       return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
-}
-#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK                       0x00ff0000
-#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT                      16
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
-{
-       return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
-}
-
-#define REG_A2XX_RB_STENCILREFMASK_BF                          0x0000210c
-#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK             0x000000ff
-#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT            0
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK            0x0000ff00
-#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT           8
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK       0x00ff0000
-#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT      16
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A2XX_RB_STENCILREFMASK                             0x0000210d
-#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK                        0x000000ff
-#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT               0
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK               0x0000ff00
-#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT              8
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK          0x00ff0000
-#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT         16
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A2XX_RB_ALPHA_REF                                  0x0000210e
-
-#define REG_A2XX_PA_CL_VPORT_XSCALE                            0x0000210f
-#define A2XX_PA_CL_VPORT_XSCALE__MASK                          0xffffffff
-#define A2XX_PA_CL_VPORT_XSCALE__SHIFT                         0
-static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_XOFFSET                           0x00002110
-#define A2XX_PA_CL_VPORT_XOFFSET__MASK                         0xffffffff
-#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT                                0
-static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_YSCALE                            0x00002111
-#define A2XX_PA_CL_VPORT_YSCALE__MASK                          0xffffffff
-#define A2XX_PA_CL_VPORT_YSCALE__SHIFT                         0
-static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_YOFFSET                           0x00002112
-#define A2XX_PA_CL_VPORT_YOFFSET__MASK                         0xffffffff
-#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT                                0
-static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_ZSCALE                            0x00002113
-#define A2XX_PA_CL_VPORT_ZSCALE__MASK                          0xffffffff
-#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT                         0
-static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_ZOFFSET                           0x00002114
-#define A2XX_PA_CL_VPORT_ZOFFSET__MASK                         0xffffffff
-#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT                                0
-static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
-}
-
-#define REG_A2XX_SQ_PROGRAM_CNTL                               0x00002180
-#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK                     0x000000ff
-#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT                    0
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK                     0x0000ff00
-#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT                    8
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE                       0x00010000
-#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE                       0x00020000
-#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN                         0x00040000
-#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX                     0x00080000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK             0x00f00000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT            20
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK              0x07000000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT             24
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
-{
-       return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK              0x78000000
-#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT             27
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX                     0x80000000
-
-#define REG_A2XX_SQ_CONTEXT_MISC                               0x00002181
-#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE                        0x00000001
-#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY               0x00000002
-#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK              0x0000000c
-#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT             2
-static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
-{
-       return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
-}
-#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK               0x0000ff00
-#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT              8
-static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
-{
-       return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
-}
-#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF                   0x00010000
-#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE                    0x00020000
-#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL                      0x00040000
-
-#define REG_A2XX_SQ_INTERPOLATOR_CNTL                          0x00002182
-#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK            0x0000ffff
-#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT           0
-static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
-}
-#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK       0xffff0000
-#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT      16
-static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
-{
-       return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
-}
-
-#define REG_A2XX_SQ_WRAPPING_0                                 0x00002183
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK                  0x0000000f
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT                 0
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK                  0x000000f0
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT                 4
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK                  0x00000f00
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT                 8
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK                  0x0000f000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT                 12
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK                  0x000f0000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT                 16
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK                  0x00f00000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT                 20
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK                  0x0f000000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT                 24
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK                  0xf0000000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT                 28
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
-}
-
-#define REG_A2XX_SQ_WRAPPING_1                                 0x00002184
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK                  0x0000000f
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT                 0
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK                  0x000000f0
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT                 4
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK                 0x00000f00
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT                        8
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK                 0x0000f000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT                        12
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK                 0x000f0000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT                        16
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK                 0x00f00000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT                        20
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK                 0x0f000000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT                        24
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK                 0xf0000000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT                        28
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
-{
-       return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
-}
-
-#define REG_A2XX_SQ_PS_PROGRAM                                 0x000021f6
-#define A2XX_SQ_PS_PROGRAM_BASE__MASK                          0x00000fff
-#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT                         0
-static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
-}
-#define A2XX_SQ_PS_PROGRAM_SIZE__MASK                          0x00fff000
-#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT                         12
-static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_VS_PROGRAM                                 0x000021f7
-#define A2XX_SQ_VS_PROGRAM_BASE__MASK                          0x00000fff
-#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT                         0
-static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
-}
-#define A2XX_SQ_VS_PROGRAM_SIZE__MASK                          0x00fff000
-#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT                         12
-static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
-}
-
-#define REG_A2XX_VGT_EVENT_INITIATOR                           0x000021f9
-
-#define REG_A2XX_VGT_DRAW_INITIATOR                            0x000021fc
-#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK                        0x0000003f
-#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT               0
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
-{
-       return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK            0x000000c0
-#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT           6
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
-{
-       return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK                 0x00000600
-#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT                        9
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
-       return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK               0x00000800
-#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT              11
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
-{
-       return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP                                0x00001000
-#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX                    0x00002000
-#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE      0x00004000
-#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK            0xff000000
-#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT           24
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
-{
-       return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
-}
-
-#define REG_A2XX_VGT_IMMED_DATA                                        0x000021fd
-
-#define REG_A2XX_RB_DEPTHCONTROL                               0x00002200
-#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE                    0x00000001
-#define A2XX_RB_DEPTHCONTROL_Z_ENABLE                          0x00000002
-#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE                    0x00000004
-#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE                    0x00000008
-#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK                       0x00000070
-#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT                      4
-static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE                   0x00000080
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK                 0x00000700
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT                        8
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK                 0x00003800
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT                        11
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK                        0x0001c000
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT               14
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK                        0x000e0000
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT               17
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK              0x00700000
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT             20
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK              0x03800000
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT             23
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK             0x1c000000
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT            26
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK             0xe0000000
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT            29
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
-{
-       return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
-}
-
-#define REG_A2XX_RB_BLEND_CONTROL                              0x00002201
-#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK             0x0000001f
-#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT            0
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK             0x000000e0
-#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT            5
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK            0x00001f00
-#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT           8
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK             0x001f0000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT            16
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK             0x00e00000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT            21
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK            0x1f000000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT           24
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
-{
-       return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE               0x20000000
-#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE                      0x40000000
-
-#define REG_A2XX_RB_COLORCONTROL                               0x00002202
-#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK                  0x00000007
-#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT                 0
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE                 0x00000008
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE              0x00000010
-#define A2XX_RB_COLORCONTROL_BLEND_DISABLE                     0x00000020
-#define A2XX_RB_COLORCONTROL_VOB_ENABLE                                0x00000040
-#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG                    0x00000080
-#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK                    0x00000f00
-#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT                   8
-static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK                 0x00003000
-#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT                        12
-static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK                 0x0000c000
-#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT                        14
-static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_PIXEL_FOG                         0x00010000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK       0x03000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT      24
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK       0x0c000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT      26
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK       0x30000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT      28
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK       0xc0000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT      30
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
-{
-       return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
-}
-
-#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX                                0x00002203
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK               0x00000007
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT              0
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK                  0x00000038
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT                 3
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK      0x000001c0
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT     6
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
-}
-
-#define REG_A2XX_PA_CL_CLIP_CNTL                               0x00002204
-#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE                      0x00010000
-#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA            0x00040000
-#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK           0x00080000
-#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT          19
-static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
-{
-       return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
-}
-#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT               0x00100000
-#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR                       0x00200000
-#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN                     0x00400000
-#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN                      0x00800000
-#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN                      0x01000000
-
-#define REG_A2XX_PA_SU_SC_MODE_CNTL                            0x00002205
-#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT                     0x00000001
-#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK                      0x00000002
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE                           0x00000004
-#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK                 0x00000018
-#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT                        3
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
-{
-       return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK              0x000000e0
-#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT             5
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
-{
-       return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK               0x00000700
-#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT              8
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
-{
-       return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE       0x00000800
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE                0x00001000
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE                0x00002000
-#define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE                    0x00008000
-#define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE       0x00010000
-#define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE            0x00040000
-#define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST             0x00080000
-#define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS                 0x00100000
-#define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA              0x00200000
-#define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE              0x00800000
-#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI           0x02000000
-#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE       0x04000000
-#define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS               0x10000000
-#define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS             0x20000000
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE               0x40000000
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE              0x80000000
-
-#define REG_A2XX_PA_CL_VTE_CNTL                                        0x00002206
-#define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA                  0x00000001
-#define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA                 0x00000002
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA                  0x00000004
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA                 0x00000008
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA                  0x00000010
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA                 0x00000020
-#define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT                         0x00000100
-#define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT                          0x00000200
-#define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT                         0x00000400
-#define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF                    0x00000800
-
-#define REG_A2XX_VGT_CURRENT_BIN_ID_MIN                                0x00002207
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK               0x00000007
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT              0
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK                  0x00000038
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT                 3
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK      0x000001c0
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT     6
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
-{
-       return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
-}
-
-#define REG_A2XX_RB_MODECONTROL                                        0x00002208
-#define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK                   0x00000007
-#define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT                  0
-static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
-{
-       return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
-}
-
-#define REG_A2XX_A220_RB_LRZ_VSC_CONTROL                       0x00002209
-
-#define REG_A2XX_RB_SAMPLE_POS                                 0x0000220a
-
-#define REG_A2XX_CLEAR_COLOR                                   0x0000220b
-#define A2XX_CLEAR_COLOR_RED__MASK                             0x000000ff
-#define A2XX_CLEAR_COLOR_RED__SHIFT                            0
-static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
-{
-       return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
-}
-#define A2XX_CLEAR_COLOR_GREEN__MASK                           0x0000ff00
-#define A2XX_CLEAR_COLOR_GREEN__SHIFT                          8
-static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
-{
-       return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
-}
-#define A2XX_CLEAR_COLOR_BLUE__MASK                            0x00ff0000
-#define A2XX_CLEAR_COLOR_BLUE__SHIFT                           16
-static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
-{
-       return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
-}
-#define A2XX_CLEAR_COLOR_ALPHA__MASK                           0xff000000
-#define A2XX_CLEAR_COLOR_ALPHA__SHIFT                          24
-static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
-{
-       return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
-}
-
-#define REG_A2XX_A220_GRAS_CONTROL                             0x00002210
-
-#define REG_A2XX_PA_SU_POINT_SIZE                              0x00002280
-#define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK                     0x0000ffff
-#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT                    0
-static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
-{
-       return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
-}
-#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK                      0xffff0000
-#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT                     16
-static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
-{
-       return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
-}
-
-#define REG_A2XX_PA_SU_POINT_MINMAX                            0x00002281
-#define A2XX_PA_SU_POINT_MINMAX_MIN__MASK                      0x0000ffff
-#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT                     0
-static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
-{
-       return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK                      0xffff0000
-#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT                     16
-static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
-{
-       return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A2XX_PA_SU_LINE_CNTL                               0x00002282
-#define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK                       0x0000ffff
-#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT                      0
-static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
-{
-       return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
-}
-
-#define REG_A2XX_PA_SC_LINE_STIPPLE                            0x00002283
-#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK             0x0000ffff
-#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT            0
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK             0x00ff0000
-#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT            16
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK                0x10000000
-#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT       28
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
-{
-       return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK          0x60000000
-#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT         29
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
-{
-       return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
-}
-
-#define REG_A2XX_PA_SC_VIZ_QUERY                               0x00002293
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA                     0x00000001
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK                        0x0000007e
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT               1
-static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
-}
-#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z             0x00000100
-
-#define REG_A2XX_VGT_ENHANCE                                   0x00002294
-
-#define REG_A2XX_PA_SC_LINE_CNTL                               0x00002300
-#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK                   0x0000ffff
-#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT                  0
-static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
-}
-#define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL                     0x00000100
-#define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH                 0x00000200
-#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL                                0x00000400
-
-#define REG_A2XX_PA_SC_AA_CONFIG                               0x00002301
-#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK            0x00000007
-#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT           0
-static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
-}
-#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK             0x0001e000
-#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT            13
-static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
-{
-       return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
-}
-
-#define REG_A2XX_PA_SU_VTX_CNTL                                        0x00002302
-#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK                   0x00000001
-#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT                  0
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
-{
-       return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
-}
-#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK                   0x00000006
-#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT                  1
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
-{
-       return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
-}
-#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK                   0x00000380
-#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT                  7
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
-{
-       return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ                                0x00002303
-#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK                      0xffffffff
-#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT                     0
-static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ                                0x00002304
-#define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK                      0xffffffff
-#define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT                     0
-static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ                                0x00002305
-#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK                      0xffffffff
-#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT                     0
-static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ                                0x00002306
-#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK                      0xffffffff
-#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT                     0
-static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
-{
-       return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
-}
-
-#define REG_A2XX_SQ_VS_CONST                                   0x00002307
-#define A2XX_SQ_VS_CONST_BASE__MASK                            0x000001ff
-#define A2XX_SQ_VS_CONST_BASE__SHIFT                           0
-static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
-}
-#define A2XX_SQ_VS_CONST_SIZE__MASK                            0x001ff000
-#define A2XX_SQ_VS_CONST_SIZE__SHIFT                           12
-static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_PS_CONST                                   0x00002308
-#define A2XX_SQ_PS_CONST_BASE__MASK                            0x000001ff
-#define A2XX_SQ_PS_CONST_BASE__SHIFT                           0
-static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
-}
-#define A2XX_SQ_PS_CONST_SIZE__MASK                            0x001ff000
-#define A2XX_SQ_PS_CONST_SIZE__SHIFT                           12
-static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_DEBUG_MISC_0                               0x00002309
-
-#define REG_A2XX_SQ_DEBUG_MISC_1                               0x0000230a
-
-#define REG_A2XX_PA_SC_AA_MASK                                 0x00002312
-
-#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL                   0x00002316
-#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
-#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT        0
-static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
-{
-       return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
-}
-
-#define REG_A2XX_VGT_OUT_DEALLOC_CNTL                          0x00002317
-#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK           0x00000003
-#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT          0
-static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
-{
-       return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
-}
-
-#define REG_A2XX_RB_COPY_CONTROL                               0x00002318
-#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK          0x00000007
-#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT         0
-static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
-{
-       return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
-}
-#define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE                        0x00000008
-#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK                  0x000000f0
-#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT                 4
-static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
-{
-       return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
-}
-
-#define REG_A2XX_RB_COPY_DEST_BASE                             0x00002319
-
-#define REG_A2XX_RB_COPY_DEST_PITCH                            0x0000231a
-#define A2XX_RB_COPY_DEST_PITCH__MASK                          0xffffffff
-#define A2XX_RB_COPY_DEST_PITCH__SHIFT                         0
-static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
-{
-       assert(!(val & 0x1f));
-       return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
-}
-
-#define REG_A2XX_RB_COPY_DEST_INFO                             0x0000231b
-#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK               0x00000007
-#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT              0
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_LINEAR                          0x00000008
-#define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK                    0x000000f0
-#define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                   4
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_SWAP__MASK                      0x00000300
-#define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT                     8
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK               0x00000c00
-#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT              10
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK               0x00003000
-#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT              12
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_WRITE_RED                       0x00004000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN                     0x00008000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE                      0x00010000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA                     0x00020000
-
-#define REG_A2XX_RB_COPY_DEST_OFFSET                           0x0000231c
-#define A2XX_RB_COPY_DEST_OFFSET_X__MASK                       0x00001fff
-#define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT                      0
-static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
-}
-#define A2XX_RB_COPY_DEST_OFFSET_Y__MASK                       0x03ffe000
-#define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT                      13
-static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
-{
-       return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
-}
-
-#define REG_A2XX_RB_DEPTH_CLEAR                                        0x0000231d
-
-#define REG_A2XX_RB_SAMPLE_COUNT_CTL                           0x00002324
-
-#define REG_A2XX_RB_COLOR_DEST_MASK                            0x00002326
-
-#define REG_A2XX_A225_GRAS_UCP0X                               0x00002340
-
-#define REG_A2XX_A225_GRAS_UCP5W                               0x00002357
-
-#define REG_A2XX_A225_GRAS_UCP_ENABLED                         0x00002360
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE                 0x00002380
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET                 0x00002383
-
-#define REG_A2XX_SQ_CONSTANT_0                                 0x00004000
-
-#define REG_A2XX_SQ_FETCH_0                                    0x00004800
-
-#define REG_A2XX_SQ_CF_BOOLEANS                                        0x00004900
-
-#define REG_A2XX_SQ_CF_LOOP                                    0x00004908
-
-#define REG_A2XX_COHER_SIZE_PM4                                        0x00000a29
-
-#define REG_A2XX_COHER_BASE_PM4                                        0x00000a2a
-
-#define REG_A2XX_COHER_STATUS_PM4                              0x00000a2b
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT                     0x00000c88
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT                     0x00000c89
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT                     0x00000c8a
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT                     0x00000c8b
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW                                0x00000c8c
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_HI                         0x00000c8d
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW                                0x00000c8e
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_HI                         0x00000c8f
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW                                0x00000c90
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_HI                         0x00000c91
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW                                0x00000c92
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_HI                         0x00000c93
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT                     0x00000c98
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW                                0x00000c99
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_HI                         0x00000c9a
-
-#define REG_A2XX_VGT_PERFCOUNTER0_SELECT                       0x00000c48
-
-#define REG_A2XX_VGT_PERFCOUNTER1_SELECT                       0x00000c49
-
-#define REG_A2XX_VGT_PERFCOUNTER2_SELECT                       0x00000c4a
-
-#define REG_A2XX_VGT_PERFCOUNTER3_SELECT                       0x00000c4b
-
-#define REG_A2XX_VGT_PERFCOUNTER0_LOW                          0x00000c4c
-
-#define REG_A2XX_VGT_PERFCOUNTER1_LOW                          0x00000c4e
-
-#define REG_A2XX_VGT_PERFCOUNTER2_LOW                          0x00000c50
-
-#define REG_A2XX_VGT_PERFCOUNTER3_LOW                          0x00000c52
-
-#define REG_A2XX_VGT_PERFCOUNTER0_HI                           0x00000c4d
-
-#define REG_A2XX_VGT_PERFCOUNTER1_HI                           0x00000c4f
-
-#define REG_A2XX_VGT_PERFCOUNTER2_HI                           0x00000c51
-
-#define REG_A2XX_VGT_PERFCOUNTER3_HI                           0x00000c53
-
-#define REG_A2XX_TCR_PERFCOUNTER0_SELECT                       0x00000e05
-
-#define REG_A2XX_TCR_PERFCOUNTER1_SELECT                       0x00000e08
-
-#define REG_A2XX_TCR_PERFCOUNTER0_HI                           0x00000e06
-
-#define REG_A2XX_TCR_PERFCOUNTER1_HI                           0x00000e09
-
-#define REG_A2XX_TCR_PERFCOUNTER0_LOW                          0x00000e07
-
-#define REG_A2XX_TCR_PERFCOUNTER1_LOW                          0x00000e0a
-
-#define REG_A2XX_TP0_PERFCOUNTER0_SELECT                       0x00000e1f
-
-#define REG_A2XX_TP0_PERFCOUNTER0_HI                           0x00000e20
-
-#define REG_A2XX_TP0_PERFCOUNTER0_LOW                          0x00000e21
-
-#define REG_A2XX_TP0_PERFCOUNTER1_SELECT                       0x00000e22
-
-#define REG_A2XX_TP0_PERFCOUNTER1_HI                           0x00000e23
-
-#define REG_A2XX_TP0_PERFCOUNTER1_LOW                          0x00000e24
-
-#define REG_A2XX_TCM_PERFCOUNTER0_SELECT                       0x00000e54
-
-#define REG_A2XX_TCM_PERFCOUNTER1_SELECT                       0x00000e57
-
-#define REG_A2XX_TCM_PERFCOUNTER0_HI                           0x00000e55
-
-#define REG_A2XX_TCM_PERFCOUNTER1_HI                           0x00000e58
-
-#define REG_A2XX_TCM_PERFCOUNTER0_LOW                          0x00000e56
-
-#define REG_A2XX_TCM_PERFCOUNTER1_LOW                          0x00000e59
-
-#define REG_A2XX_TCF_PERFCOUNTER0_SELECT                       0x00000e5a
-
-#define REG_A2XX_TCF_PERFCOUNTER1_SELECT                       0x00000e5d
-
-#define REG_A2XX_TCF_PERFCOUNTER2_SELECT                       0x00000e60
-
-#define REG_A2XX_TCF_PERFCOUNTER3_SELECT                       0x00000e63
-
-#define REG_A2XX_TCF_PERFCOUNTER4_SELECT                       0x00000e66
-
-#define REG_A2XX_TCF_PERFCOUNTER5_SELECT                       0x00000e69
-
-#define REG_A2XX_TCF_PERFCOUNTER6_SELECT                       0x00000e6c
-
-#define REG_A2XX_TCF_PERFCOUNTER7_SELECT                       0x00000e6f
-
-#define REG_A2XX_TCF_PERFCOUNTER8_SELECT                       0x00000e72
-
-#define REG_A2XX_TCF_PERFCOUNTER9_SELECT                       0x00000e75
-
-#define REG_A2XX_TCF_PERFCOUNTER10_SELECT                      0x00000e78
-
-#define REG_A2XX_TCF_PERFCOUNTER11_SELECT                      0x00000e7b
-
-#define REG_A2XX_TCF_PERFCOUNTER0_HI                           0x00000e5b
-
-#define REG_A2XX_TCF_PERFCOUNTER1_HI                           0x00000e5e
-
-#define REG_A2XX_TCF_PERFCOUNTER2_HI                           0x00000e61
-
-#define REG_A2XX_TCF_PERFCOUNTER3_HI                           0x00000e64
-
-#define REG_A2XX_TCF_PERFCOUNTER4_HI                           0x00000e67
-
-#define REG_A2XX_TCF_PERFCOUNTER5_HI                           0x00000e6a
-
-#define REG_A2XX_TCF_PERFCOUNTER6_HI                           0x00000e6d
-
-#define REG_A2XX_TCF_PERFCOUNTER7_HI                           0x00000e70
-
-#define REG_A2XX_TCF_PERFCOUNTER8_HI                           0x00000e73
-
-#define REG_A2XX_TCF_PERFCOUNTER9_HI                           0x00000e76
-
-#define REG_A2XX_TCF_PERFCOUNTER10_HI                          0x00000e79
-
-#define REG_A2XX_TCF_PERFCOUNTER11_HI                          0x00000e7c
-
-#define REG_A2XX_TCF_PERFCOUNTER0_LOW                          0x00000e5c
-
-#define REG_A2XX_TCF_PERFCOUNTER1_LOW                          0x00000e5f
-
-#define REG_A2XX_TCF_PERFCOUNTER2_LOW                          0x00000e62
-
-#define REG_A2XX_TCF_PERFCOUNTER3_LOW                          0x00000e65
-
-#define REG_A2XX_TCF_PERFCOUNTER4_LOW                          0x00000e68
-
-#define REG_A2XX_TCF_PERFCOUNTER5_LOW                          0x00000e6b
-
-#define REG_A2XX_TCF_PERFCOUNTER6_LOW                          0x00000e6e
-
-#define REG_A2XX_TCF_PERFCOUNTER7_LOW                          0x00000e71
-
-#define REG_A2XX_TCF_PERFCOUNTER8_LOW                          0x00000e74
-
-#define REG_A2XX_TCF_PERFCOUNTER9_LOW                          0x00000e77
-
-#define REG_A2XX_TCF_PERFCOUNTER10_LOW                         0x00000e7a
-
-#define REG_A2XX_TCF_PERFCOUNTER11_LOW                         0x00000e7d
-
-#define REG_A2XX_SQ_PERFCOUNTER0_SELECT                                0x00000dc8
-
-#define REG_A2XX_SQ_PERFCOUNTER1_SELECT                                0x00000dc9
-
-#define REG_A2XX_SQ_PERFCOUNTER2_SELECT                                0x00000dca
-
-#define REG_A2XX_SQ_PERFCOUNTER3_SELECT                                0x00000dcb
-
-#define REG_A2XX_SQ_PERFCOUNTER0_LOW                           0x00000dcc
-
-#define REG_A2XX_SQ_PERFCOUNTER0_HI                            0x00000dcd
-
-#define REG_A2XX_SQ_PERFCOUNTER1_LOW                           0x00000dce
-
-#define REG_A2XX_SQ_PERFCOUNTER1_HI                            0x00000dcf
-
-#define REG_A2XX_SQ_PERFCOUNTER2_LOW                           0x00000dd0
-
-#define REG_A2XX_SQ_PERFCOUNTER2_HI                            0x00000dd1
-
-#define REG_A2XX_SQ_PERFCOUNTER3_LOW                           0x00000dd2
-
-#define REG_A2XX_SQ_PERFCOUNTER3_HI                            0x00000dd3
-
-#define REG_A2XX_SX_PERFCOUNTER0_SELECT                                0x00000dd4
-
-#define REG_A2XX_SX_PERFCOUNTER0_LOW                           0x00000dd8
-
-#define REG_A2XX_SX_PERFCOUNTER0_HI                            0x00000dd9
-
-#define REG_A2XX_MH_PERFCOUNTER0_SELECT                                0x00000a46
-
-#define REG_A2XX_MH_PERFCOUNTER1_SELECT                                0x00000a4a
-
-#define REG_A2XX_MH_PERFCOUNTER0_CONFIG                                0x00000a47
-
-#define REG_A2XX_MH_PERFCOUNTER1_CONFIG                                0x00000a4b
-
-#define REG_A2XX_MH_PERFCOUNTER0_LOW                           0x00000a48
-
-#define REG_A2XX_MH_PERFCOUNTER1_LOW                           0x00000a4c
-
-#define REG_A2XX_MH_PERFCOUNTER0_HI                            0x00000a49
-
-#define REG_A2XX_MH_PERFCOUNTER1_HI                            0x00000a4d
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                      0x00000395
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_LO                          0x00000397
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_HI                          0x00000398
-
-#define REG_A2XX_CP_PERFCOUNTER_SELECT                         0x00000445
-
-#define REG_A2XX_CP_PERFCOUNTER_LO                             0x00000446
-
-#define REG_A2XX_CP_PERFCOUNTER_HI                             0x00000447
-
-#define REG_A2XX_RB_PERFCOUNTER0_SELECT                                0x00000f04
-
-#define REG_A2XX_RB_PERFCOUNTER0_LOW                           0x00000f08
-
-#define REG_A2XX_RB_PERFCOUNTER0_HI                            0x00000f09
-
-#define REG_A2XX_SQ_TEX_0                                      0x00000000
-#define A2XX_SQ_TEX_0_TYPE__MASK                               0x00000003
-#define A2XX_SQ_TEX_0_TYPE__SHIFT                              0
-static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
-{
-       return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_X__MASK                             0x0000000c
-#define A2XX_SQ_TEX_0_SIGN_X__SHIFT                            2
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
-{
-       return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_Y__MASK                             0x00000030
-#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT                            4
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
-{
-       return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_Z__MASK                             0x000000c0
-#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT                            6
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
-{
-       return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_W__MASK                             0x00000300
-#define A2XX_SQ_TEX_0_SIGN_W__SHIFT                            8
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
-{
-       return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_X__MASK                            0x00001c00
-#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT                           10
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
-{
-       return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_Y__MASK                            0x0000e000
-#define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT                           13
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
-{
-       return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_Z__MASK                            0x00070000
-#define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT                           16
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
-{
-       return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
-}
-#define A2XX_SQ_TEX_0_PITCH__MASK                              0x7fc00000
-#define A2XX_SQ_TEX_0_PITCH__SHIFT                             22
-static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
-{
-       assert(!(val & 0x1f));
-       return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
-}
-#define A2XX_SQ_TEX_0_TILED                                    0x00000002
-
-#define REG_A2XX_SQ_TEX_1                                      0x00000001
-#define A2XX_SQ_TEX_1_FORMAT__MASK                             0x0000003f
-#define A2XX_SQ_TEX_1_FORMAT__SHIFT                            0
-static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
-{
-       return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK;
-}
-#define A2XX_SQ_TEX_1_ENDIANNESS__MASK                         0x000000c0
-#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT                                6
-static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
-{
-       return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK;
-}
-#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK                       0x00000300
-#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT                      8
-static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK;
-}
-#define A2XX_SQ_TEX_1_STACKED                                  0x00000400
-#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK                       0x00000800
-#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT                      11
-static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
-{
-       return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK;
-}
-#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK                       0xfffff000
-#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT                      12
-static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
-{
-       assert(!(val & 0xfff));
-       return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_2                                      0x00000002
-#define A2XX_SQ_TEX_2_WIDTH__MASK                              0x00001fff
-#define A2XX_SQ_TEX_2_WIDTH__SHIFT                             0
-static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
-}
-#define A2XX_SQ_TEX_2_HEIGHT__MASK                             0x03ffe000
-#define A2XX_SQ_TEX_2_HEIGHT__SHIFT                            13
-static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
-}
-#define A2XX_SQ_TEX_2_DEPTH__MASK                              0xfc000000
-#define A2XX_SQ_TEX_2_DEPTH__SHIFT                             26
-static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_3                                      0x00000003
-#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK                         0x00000001
-#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT                                0
-static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
-{
-       return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_X__MASK                             0x0000000e
-#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT                            1
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
-{
-       return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_Y__MASK                             0x00000070
-#define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT                            4
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
-{
-       return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_Z__MASK                             0x00000380
-#define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT                            7
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
-{
-       return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_W__MASK                             0x00001c00
-#define A2XX_SQ_TEX_3_SWIZ_W__SHIFT                            10
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
-{
-       return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
-}
-#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK                         0x0007e000
-#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT                                13
-static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
-}
-#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK                      0x00180000
-#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT                     19
-static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK                      0x00600000
-#define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT                     21
-static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_MIP_FILTER__MASK                         0x01800000
-#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT                                23
-static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK                       0x0e000000
-#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT                      25
-static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK                                0x80000000
-#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT                       31
-static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_4                                      0x00000004
-#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK                     0x00000001
-#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT                    0
-static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK                     0x00000002
-#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT                    1
-static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
-{
-       return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK                      0x0000003c
-#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT                     2
-static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK;
-}
-#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK                      0x000003c0
-#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT                     6
-static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK;
-}
-#define A2XX_SQ_TEX_4_MAX_ANISO_WALK                           0x00000400
-#define A2XX_SQ_TEX_4_MIN_ANISO_WALK                           0x00000800
-#define A2XX_SQ_TEX_4_LOD_BIAS__MASK                           0x003ff000
-#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT                          12
-static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
-{
-       return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK;
-}
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK                  0x07c00000
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT                 22
-static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK;
-}
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK                  0xf8000000
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT                 27
-static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_5                                      0x00000005
-#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK                       0x00000003
-#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT                      0
-static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
-{
-       return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK;
-}
-#define A2XX_SQ_TEX_5_FORCE_BCW_MAX                            0x00000004
-#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK                          0x00000018
-#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT                         3
-static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
-{
-       return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK;
-}
-#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK                         0x000001e0
-#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT                                5
-static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
-{
-       return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK;
-}
-#define A2XX_SQ_TEX_5_DIMENSION__MASK                          0x00000600
-#define A2XX_SQ_TEX_5_DIMENSION__SHIFT                         9
-static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
-{
-       return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK;
-}
-#define A2XX_SQ_TEX_5_PACKED_MIPS                              0x00000800
-#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK                                0xfffff000
-#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT                       12
-static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
-{
-       assert(!(val & 0xfff));
-       return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
-}
-
-
-#endif /* A2XX_XML */
diff --git a/src/freedreno/registers/a3xx.xml b/src/freedreno/registers/a3xx.xml
new file mode 100644 (file)
index 0000000..bf93b0c
--- /dev/null
@@ -0,0 +1,1754 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<enum name="a3xx_tile_mode">
+       <value name="LINEAR" value="0"/>
+       <value name="TILE_4X4" value="1"/>    <!-- "normal" case for textures -->
+       <value name="TILE_32X32" value="2"/>  <!-- only used in GMEM -->
+       <value name="TILE_4X2" value="3"/>    <!-- only used for CrCb -->
+</enum>
+
+<enum name="a3xx_state_block_id">
+       <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
+       <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
+       <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
+       <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
+</enum>
+
+<enum name="a3xx_cache_opcode">
+       <value name="INVALIDATE" value="1"/>
+</enum>
+
+<enum name="a3xx_vtx_fmt">
+       <value name="VFMT_32_FLOAT" value="0x0"/>
+       <value name="VFMT_32_32_FLOAT" value="0x1"/>
+       <value name="VFMT_32_32_32_FLOAT" value="0x2"/>
+       <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
+
+       <value name="VFMT_16_FLOAT" value="0x4"/>
+       <value name="VFMT_16_16_FLOAT" value="0x5"/>
+       <value name="VFMT_16_16_16_FLOAT" value="0x6"/>
+       <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
+
+       <value name="VFMT_32_FIXED" value="0x8"/>
+       <value name="VFMT_32_32_FIXED" value="0x9"/>
+       <value name="VFMT_32_32_32_FIXED" value="0xa"/>
+       <value name="VFMT_32_32_32_32_FIXED" value="0xb"/>
+
+       <value name="VFMT_16_SINT" value="0x10"/>
+       <value name="VFMT_16_16_SINT" value="0x11"/>
+       <value name="VFMT_16_16_16_SINT" value="0x12"/>
+       <value name="VFMT_16_16_16_16_SINT" value="0x13"/>
+       <value name="VFMT_16_UINT" value="0x14"/>
+       <value name="VFMT_16_16_UINT" value="0x15"/>
+       <value name="VFMT_16_16_16_UINT" value="0x16"/>
+       <value name="VFMT_16_16_16_16_UINT" value="0x17"/>
+       <value name="VFMT_16_SNORM" value="0x18"/>
+       <value name="VFMT_16_16_SNORM" value="0x19"/>
+       <value name="VFMT_16_16_16_SNORM" value="0x1a"/>
+       <value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>
+       <value name="VFMT_16_UNORM" value="0x1c"/>
+       <value name="VFMT_16_16_UNORM" value="0x1d"/>
+       <value name="VFMT_16_16_16_UNORM" value="0x1e"/>
+       <value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>
+
+       <!-- seems to be no NORM variants for 32bit.. -->
+       <value name="VFMT_32_UINT" value="0x20"/>
+       <value name="VFMT_32_32_UINT" value="0x21"/>
+       <value name="VFMT_32_32_32_UINT" value="0x22"/>
+       <value name="VFMT_32_32_32_32_UINT" value="0x23"/>
+       <value name="VFMT_32_SINT" value="0x24"/>
+       <value name="VFMT_32_32_SINT" value="0x25"/>
+       <value name="VFMT_32_32_32_SINT" value="0x26"/>
+       <value name="VFMT_32_32_32_32_SINT" value="0x27"/>
+
+       <value name="VFMT_8_UINT" value="0x28"/>
+       <value name="VFMT_8_8_UINT" value="0x29"/>
+       <value name="VFMT_8_8_8_UINT" value="0x2a"/>
+       <value name="VFMT_8_8_8_8_UINT" value="0x2b"/>
+       <value name="VFMT_8_UNORM" value="0x2c"/>
+       <value name="VFMT_8_8_UNORM" value="0x2d"/>
+       <value name="VFMT_8_8_8_UNORM" value="0x2e"/>
+       <value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>
+       <value name="VFMT_8_SINT" value="0x30"/>
+       <value name="VFMT_8_8_SINT" value="0x31"/>
+       <value name="VFMT_8_8_8_SINT" value="0x32"/>
+       <value name="VFMT_8_8_8_8_SINT" value="0x33"/>
+       <value name="VFMT_8_SNORM" value="0x34"/>
+       <value name="VFMT_8_8_SNORM" value="0x35"/>
+       <value name="VFMT_8_8_8_SNORM" value="0x36"/>
+       <value name="VFMT_8_8_8_8_SNORM" value="0x37"/>
+       <value name="VFMT_10_10_10_2_UINT" value="0x38"/>
+       <value name="VFMT_10_10_10_2_UNORM" value="0x39"/>
+       <value name="VFMT_10_10_10_2_SINT" value="0x3a"/>
+       <value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>
+       <value name="VFMT_2_10_10_10_UINT" value="0x3c"/>
+       <value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>
+       <value name="VFMT_2_10_10_10_SINT" value="0x3e"/>
+       <value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>
+</enum>
+
+<enum name="a3xx_tex_fmt">
+       <value name="TFMT_5_6_5_UNORM" value="0x4"/>
+       <value name="TFMT_5_5_5_1_UNORM" value="0x5"/>
+       <value name="TFMT_4_4_4_4_UNORM" value="0x7"/>
+       <value name="TFMT_Z16_UNORM" value="0x9"/>
+       <value name="TFMT_X8Z24_UNORM" value="0xa"/>
+       <value name="TFMT_Z32_FLOAT" value="0xb"/>
+
+       <!--
+               The NV12 tiled/linear formats seem to require gang'd sampler
+               slots (ie. sampler state N plus N+1) for Y and UV planes.
+               They fetch yuv in single sam instruction, but still require
+               colorspace conversion in the shader.
+        -->
+       <value name="TFMT_UV_64X32" value="0x10"/>
+       <value name="TFMT_VU_64X32" value="0x11"/>
+       <value name="TFMT_Y_64X32" value="0x12"/>
+       <value name="TFMT_NV12_64X32" value="0x13"/>
+       <value name="TFMT_UV_LINEAR" value="0x14"/>
+       <value name="TFMT_VU_LINEAR" value="0x15"/>
+       <value name="TFMT_Y_LINEAR" value="0x16"/>
+       <value name="TFMT_NV12_LINEAR" value="0x17"/>
+       <value name="TFMT_I420_Y" value="0x18"/>
+       <value name="TFMT_I420_U" value="0x1a"/>
+       <value name="TFMT_I420_V" value="0x1b"/>
+
+       <value name="TFMT_ATC_RGB" value="0x20"/>
+       <value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>
+       <value name="TFMT_ETC1" value="0x22"/>
+       <value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>
+
+       <value name="TFMT_DXT1" value="0x24"/>
+       <value name="TFMT_DXT3" value="0x25"/>
+       <value name="TFMT_DXT5" value="0x26"/>
+
+       <value name="TFMT_2_10_10_10_UNORM" value="0x28"/>
+       <value name="TFMT_10_10_10_2_UNORM" value="0x29"/>
+       <value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>
+       <value name="TFMT_11_11_10_FLOAT" value="0x2b"/>
+       <value name="TFMT_A8_UNORM" value="0x2c"/>    <!-- GL_ALPHA -->
+       <value name="TFMT_L8_UNORM" value="0x2d"/>
+       <value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->
+
+       <!--
+               NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way
+               to float16, float32.. but they seem to use non-standard swizzle too..
+               perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,
+               0xn3 for 1, 2, 3, 4 components respectively..
+
+               Only formats filled in below are the ones that have been observed by
+               the blob or tested.. you can guess what the missing ones are..
+        -->
+
+       <value name="TFMT_8_UNORM" value="0x30"/>     <!-- GL_LUMINANCE -->
+       <value name="TFMT_8_8_UNORM" value="0x31"/>
+       <value name="TFMT_8_8_8_UNORM" value="0x32"/>
+       <value name="TFMT_8_8_8_8_UNORM" value="0x33"/>
+
+       <value name="TFMT_8_SNORM" value="0x34"/>
+       <value name="TFMT_8_8_SNORM" value="0x35"/>
+       <value name="TFMT_8_8_8_SNORM" value="0x36"/>
+       <value name="TFMT_8_8_8_8_SNORM" value="0x37"/>
+
+       <value name="TFMT_8_UINT" value="0x38"/>
+       <value name="TFMT_8_8_UINT" value="0x39"/>
+       <value name="TFMT_8_8_8_UINT" value="0x3a"/>
+       <value name="TFMT_8_8_8_8_UINT" value="0x3b"/>
+
+       <value name="TFMT_8_SINT" value="0x3c"/>
+       <value name="TFMT_8_8_SINT" value="0x3d"/>
+       <value name="TFMT_8_8_8_SINT" value="0x3e"/>
+       <value name="TFMT_8_8_8_8_SINT" value="0x3f"/>
+
+       <value name="TFMT_16_FLOAT" value="0x40"/>
+       <value name="TFMT_16_16_FLOAT" value="0x41"/>
+       <!-- TFMT_FLOAT_16_16_16 -->
+       <value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>
+
+       <value name="TFMT_16_UINT" value="0x44"/>
+       <value name="TFMT_16_16_UINT" value="0x45"/>
+       <value name="TFMT_16_16_16_16_UINT" value="0x47"/>
+
+       <value name="TFMT_16_SINT" value="0x48"/>
+       <value name="TFMT_16_16_SINT" value="0x49"/>
+       <value name="TFMT_16_16_16_16_SINT" value="0x4b"/>
+
+       <value name="TFMT_16_UNORM" value="0x4c"/>
+       <value name="TFMT_16_16_UNORM" value="0x4d"/>
+       <value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>
+
+       <value name="TFMT_16_SNORM" value="0x50"/>
+       <value name="TFMT_16_16_SNORM" value="0x51"/>
+       <value name="TFMT_16_16_16_16_SNORM" value="0x53"/>
+
+       <value name="TFMT_32_FLOAT" value="0x54"/>
+       <value name="TFMT_32_32_FLOAT" value="0x55"/>
+       <!-- TFMT_32_32_32_FLOAT -->
+       <value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>
+
+       <value name="TFMT_32_UINT" value="0x58"/>
+       <value name="TFMT_32_32_UINT" value="0x59"/>
+       <value name="TFMT_32_32_32_32_UINT" value="0x5b"/>
+
+       <value name="TFMT_32_SINT" value="0x5c"/>
+       <value name="TFMT_32_32_SINT" value="0x5d"/>
+       <value name="TFMT_32_32_32_32_SINT" value="0x5f"/>
+
+       <value name="TFMT_2_10_10_10_UINT" value="0x60"/>
+       <value name="TFMT_10_10_10_2_UINT" value="0x61"/>
+
+       <value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>
+       <value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>
+       <value name="TFMT_ETC2_R11_SNORM" value="0x72"/>
+       <value name="TFMT_ETC2_R11_UNORM" value="0x73"/>
+       <value name="TFMT_ETC2_RGBA8" value="0x74"/>
+       <value name="TFMT_ETC2_RGB8A1" value="0x75"/>
+       <value name="TFMT_ETC2_RGB8" value="0x76"/>
+</enum>
+
+<enum name="a3xx_tex_fetchsize">
+       <doc>
+               Size pixel to fetch, in bytes.  Doesn't seem to be required, setting
+               it to 0x0 seems to work ok, but may be less optimal.
+       </doc>
+       <value name="TFETCH_DISABLE" value="0"/>
+       <value name="TFETCH_1_BYTE"  value="1"/>
+       <value name="TFETCH_2_BYTE"  value="2"/>
+       <value name="TFETCH_4_BYTE"  value="3"/>
+       <value name="TFETCH_8_BYTE"  value="4"/>
+       <value name="TFETCH_16_BYTE" value="5"/>
+</enum>
+
+<enum name="a3xx_color_fmt">
+       <value name="RB_R5G6B5_UNORM"       value="0x00"/>
+       <value name="RB_R5G5B5A1_UNORM"     value="0x01"/>
+       <value name="RB_R4G4B4A4_UNORM"     value="0x03"/>
+       <value name="RB_R8G8B8_UNORM"       value="0x04"/>
+       <value name="RB_R8G8B8A8_UNORM"     value="0x08"/>
+       <value name="RB_R8G8B8A8_SNORM"     value="0x09"/>
+       <value name="RB_R8G8B8A8_UINT"      value="0x0a"/>
+       <value name="RB_R8G8B8A8_SINT"      value="0x0b"/>
+       <value name="RB_R8G8_UNORM"         value="0x0c"/>
+       <value name="RB_R8G8_SNORM"         value="0x0d"/>
+       <value name="RB_R8_UINT"            value="0x0e"/> <!-- also used for R8G8_UINT? -->
+       <value name="RB_R8_SINT"            value="0x0f"/> <!-- also used for R8G8_SINT? -->
+       <value name="RB_R10G10B10A2_UNORM"  value="0x10"/>
+       <value name="RB_A2R10G10B10_UNORM"  value="0x11"/>
+       <value name="RB_R10G10B10A2_UINT"   value="0x12"/>
+       <value name="RB_A2R10G10B10_UINT"   value="0x13"/>
+
+       <value name="RB_A8_UNORM"           value="0x14"/>
+       <value name="RB_R8_UNORM"           value="0x15"/>
+
+       <value name="RB_R16_FLOAT"          value="0x18"/>
+       <value name="RB_R16G16_FLOAT"       value="0x19"/>
+       <value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->
+       <value name="RB_R11G11B10_FLOAT"    value="0x1c"/>
+
+       <value name="RB_R16_SNORM"          value="0x20"/>
+       <value name="RB_R16G16_SNORM"       value="0x21"/>
+       <value name="RB_R16G16B16A16_SNORM" value="0x23"/>
+
+       <value name="RB_R16_UNORM"          value="0x24"/>
+       <value name="RB_R16G16_UNORM"       value="0x25"/>
+       <value name="RB_R16G16B16A16_UNORM" value="0x27"/>
+
+       <value name="RB_R16_SINT"           value="0x28"/>
+       <value name="RB_R16G16_SINT"        value="0x29"/>
+       <value name="RB_R16G16B16A16_SINT"  value="0x2b"/>
+
+       <value name="RB_R16_UINT"           value="0x2c"/>
+       <value name="RB_R16G16_UINT"        value="0x2d"/>
+       <value name="RB_R16G16B16A16_UINT"  value="0x2f"/>
+
+       <value name="RB_R32_FLOAT"          value="0x30"/>
+       <value name="RB_R32G32_FLOAT"       value="0x31"/>
+       <value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->
+
+       <value name="RB_R32_SINT"           value="0x34"/>
+       <value name="RB_R32G32_SINT"        value="0x35"/>
+       <value name="RB_R32G32B32A32_SINT"  value="0x37"/>
+
+       <value name="RB_R32_UINT"           value="0x38"/>
+       <value name="RB_R32G32_UINT"        value="0x39"/>
+       <value name="RB_R32G32B32A32_UINT"  value="0x3b"/>
+</enum>
+
+<enum name="a3xx_cp_perfcounter_select">
+       <value value="0x00" name="CP_ALWAYS_COUNT"/>
+       <value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>
+       <value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>
+       <value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>
+       <value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>
+       <value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>
+       <value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>
+       <value value="0x0c" name="CP_RESERVED_12"/>
+       <value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>
+       <value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>
+       <value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>
+       <value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>
+       <value value="0x11" name="CP_RESERVED_17"/>
+       <value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>
+       <value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>
+       <value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>
+       <value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>
+       <value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>
+       <value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>
+       <value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>
+       <value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>
+       <value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>
+       <value value="0x29" name="CP_ME_BUSY_CLOCKS"/>
+       <value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>
+       <value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>
+       <value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>
+       <value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>
+       <value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>
+       <value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>
+       <value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>
+</enum>
+
+<enum name="a3xx_gras_tse_perfcounter_select">
+       <value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>
+       <value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>
+       <value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>
+       <value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>
+       <value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>
+       <value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>
+       <value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>
+       <value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>
+       <value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>
+       <value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>
+       <value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>
+       <value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>
+       <value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>
+       <value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>
+       <value value="0x0e" name="GRAS_TSERASPERF_STALL"/>
+</enum>
+
+<enum name="a3xx_gras_ras_perfcounter_select">
+       <value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>
+       <value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>
+       <value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>
+       <value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>
+       <value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>
+       <value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>
+       <value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>
+</enum>
+
+<enum name="a3xx_hlsq_perfcounter_select">
+       <value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>
+       <value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>
+       <value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>
+       <value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>
+       <value value="0x04" name="HLSQ_PERF_TP_STATE"/>
+       <value value="0x05" name="HLSQ_PERF_QUADS"/>
+       <value value="0x06" name="HLSQ_PERF_PIXELS"/>
+       <value value="0x07" name="HLSQ_PERF_VERTICES"/>
+       <value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>
+       <value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>
+       <value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>
+       <value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>
+       <value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>
+       <value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>
+       <value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>
+       <value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>
+       <value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>
+       <value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>
+       <value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>
+       <value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>
+       <value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>
+       <value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>
+       <value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>
+       <value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>
+       <value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>
+       <value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>
+       <value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>
+       <value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>
+       <value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>
+</enum>
+
+<enum name="a3xx_pc_perfcounter_select">
+       <value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>
+       <value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>
+       <value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>
+       <value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>
+       <value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>
+       <value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>
+       <value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>
+       <value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>
+       <value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>
+       <value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>
+       <value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>
+       <value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>
+       <value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>
+</enum>
+
+<enum name="a3xx_rb_perfcounter_select">
+       <value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>
+       <value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>
+       <value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>
+       <value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>
+       <value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>
+       <value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>
+       <value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>
+       <value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>
+       <value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>
+       <value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>
+       <value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>
+       <value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>
+       <value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>
+       <value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>
+       <value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>
+       <value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>
+       <value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>
+</enum>
+
+<enum name="a3xx_rbbm_perfcounter_select">
+       <value value="0" name="RBBM_ALAWYS_ON"/>
+       <value value="1" name="RBBM_VBIF_BUSY"/>
+       <value value="2" name="RBBM_TSE_BUSY"/>
+       <value value="3" name="RBBM_RAS_BUSY"/>
+       <value value="4" name="RBBM_PC_DCALL_BUSY"/>
+       <value value="5" name="RBBM_PC_VSD_BUSY"/>
+       <value value="6" name="RBBM_VFD_BUSY"/>
+       <value value="7" name="RBBM_VPC_BUSY"/>
+       <value value="8" name="RBBM_UCHE_BUSY"/>
+       <value value="9" name="RBBM_VSC_BUSY"/>
+       <value value="10" name="RBBM_HLSQ_BUSY"/>
+       <value value="11" name="RBBM_ANY_RB_BUSY"/>
+       <value value="12" name="RBBM_ANY_TEX_BUSY"/>
+       <value value="13" name="RBBM_ANY_USP_BUSY"/>
+       <value value="14" name="RBBM_ANY_MARB_BUSY"/>
+       <value value="15" name="RBBM_ANY_ARB_BUSY"/>
+       <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
+       <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
+       <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
+       <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
+       <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
+       <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
+       <value value="22" name="RBBM_RBBM_STATUS_MASKED"/>
+</enum>
+
+<enum name="a3xx_sp_perfcounter_select">
+       <value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>
+       <value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>
+       <value value="0x02" name="SP_LM_ATOMICS"/>
+       <value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>
+       <value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>
+       <value value="0x05" name="SP_UCHE_ATOMICS"/>
+       <value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>
+       <value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>
+       <value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>
+       <value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>
+       <value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>
+       <value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>
+       <value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>
+       <value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>
+       <value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>
+       <value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>
+       <value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>
+       <value value="0x11" name="SP_VS_INSTRUCTIONS"/>
+       <value value="0x12" name="SP_FS_INSTRUCTIONS"/>
+       <value value="0x13" name="SP_ADDR_LOCK_COUNT"/>
+       <value value="0x14" name="SP_UCHE_READ_TRANS"/>
+       <value value="0x15" name="SP_UCHE_WRITE_TRANS"/>
+       <value value="0x16" name="SP_EXPORT_VPC_TRANS"/>
+       <value value="0x17" name="SP_EXPORT_RB_TRANS"/>
+       <value value="0x18" name="SP_PIXELS_KILLED"/>
+       <value value="0x19" name="SP_ICL1_REQUESTS"/>
+       <value value="0x1a" name="SP_ICL1_MISSES"/>
+       <value value="0x1b" name="SP_ICL0_REQUESTS"/>
+       <value value="0x1c" name="SP_ICL0_MISSES"/>
+       <value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>
+       <value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>
+       <value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>
+       <value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>
+       <value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>
+       <value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>
+       <value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>
+       <value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>
+</enum>
+
+<enum name="a3xx_tp_perfcounter_select">
+       <value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>
+       <value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>
+       <value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>
+       <value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>
+       <value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>
+       <value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>
+       <value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>
+       <value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>
+       <value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>
+       <value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>
+       <value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>
+       <value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>
+       <value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>
+       <value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>
+       <value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>
+       <value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>
+       <value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>
+       <value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>
+       <value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>
+       <value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>
+       <value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>
+       <value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>
+       <value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>
+       <value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>
+       <value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>
+       <value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>
+       <value value="0x1a" name="TPL1_TPPERF_LATENCY"/>
+       <value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>
+</enum>
+
+<enum name="a3xx_vfd_perfcounter_select">
+       <value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>
+       <value value="1" name="VFD_PERF_UCHE_TRANS"/>
+       <value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>
+       <value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>
+       <value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>
+       <value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>
+       <value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>
+       <value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>
+       <value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>
+       <value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>
+</enum>
+
+<enum name="a3xx_vpc_perfcounter_select">
+       <value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>
+       <value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>
+       <value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>
+       <value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>
+       <value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>
+       <value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>
+</enum>
+
+<enum name="a3xx_uche_perfcounter_select">
+       <value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>
+       <value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>
+       <value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>
+       <value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>
+       <value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>
+       <value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>
+       <value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>
+       <value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>
+       <value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>
+       <value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>
+       <value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>
+       <value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>
+       <value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>
+       <value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>
+       <value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>
+       <value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>
+       <value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>
+       <value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>
+</enum>
+
+<enum name="a3xx_intp_mode">
+       <value name="SMOOTH" value="0"/>
+       <value name="FLAT" value="1"/>
+       <value name="ZERO" value="2"/>
+       <value name="ONE" value="3"/>
+</enum>
+
+<enum name="a3xx_repl_mode">
+       <value name="S" value="1"/>
+       <value name="T" value="2"/>
+       <value name="ONE_T" value="3"/>
+</enum>
+
+<domain name="A3XX" width="32">
+       <!-- RBBM registers -->
+       <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
+       <reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>
+       <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
+       <reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>
+       <reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>
+       <reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>
+       <reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>
+       <reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>
+       <reg32 offset="0x0022" name="RBBM_AHB_CMD"/>
+       <reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>
+       <reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>
+       <reg32 offset="0x0030" name="RBBM_STATUS">
+               <bitfield name="HI_BUSY" pos="0" type="boolean"/>
+               <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
+               <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
+               <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
+               <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
+               <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
+               <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
+               <bitfield name="RB_BUSY" pos="18" type="boolean"/>
+               <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
+               <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
+               <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
+               <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
+               <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
+               <bitfield name="SP_BUSY" pos="24" type="boolean"/>
+               <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
+               <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
+               <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
+               <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
+               <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
+               <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
+               <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
+       </reg32>
+       <!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->
+       <reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>
+       <reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
+       <reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>
+       <reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>
+       <reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>
+       <reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>
+       <reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>
+
+       <bitset name="A3XX_INT0">
+               <bitfield name="RBBM_GPU_IDLE" pos="0"/>
+               <bitfield name="RBBM_AHB_ERROR" pos="1"/>
+               <bitfield name="RBBM_REG_TIMEOUT" pos="2"/>
+               <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/>
+               <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/>
+               <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5"/>
+               <bitfield name="VFD_ERROR" pos="6"/>
+               <bitfield name="CP_SW_INT" pos="7"/>
+               <bitfield name="CP_T0_PACKET_IN_IB" pos="8"/>
+               <bitfield name="CP_OPCODE_ERROR" pos="9"/>
+               <bitfield name="CP_RESERVED_BIT_ERROR" pos="10"/>
+               <bitfield name="CP_HW_FAULT" pos="11"/>
+               <bitfield name="CP_DMA" pos="12"/>
+               <bitfield name="CP_IB2_INT" pos="13"/>
+               <bitfield name="CP_IB1_INT" pos="14"/>
+               <bitfield name="CP_RB_INT" pos="15"/>
+               <bitfield name="CP_REG_PROTECT_FAULT" pos="16"/>
+               <bitfield name="CP_RB_DONE_TS" pos="17"/>
+               <bitfield name="CP_VS_DONE_TS" pos="18"/>
+               <bitfield name="CP_PS_DONE_TS" pos="19"/>
+               <bitfield name="CACHE_FLUSH_TS" pos="20"/>
+               <bitfield name="CP_AHB_ERROR_HALT" pos="21"/>
+               <bitfield name="MISC_HANG_DETECT" pos="24"/>
+               <bitfield name="UCHE_OOB_ACCESS" pos="25"/>
+       </bitset>
+
+
+       <!--
+               set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare
+               to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
+               way for fw to raise and irq:
+        -->
+       <reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>
+       <reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>
+       <reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>
+       <reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>
+       <reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">
+               <bitfield name="ENABLE" pos="0" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>
+       <reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>
+       <reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+       <reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+       <reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>
+       <reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>
+       <reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>
+       <reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>
+       <reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>
+       <reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>
+       <reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>
+       <reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>
+       <reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>
+       <reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>
+       <reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>
+       <reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>
+       <reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>
+       <reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>
+       <reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>
+       <reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>
+       <reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>
+       <reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>
+       <reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>
+       <reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>
+       <reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>
+       <reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>
+       <reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>
+       <reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>
+       <reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>
+       <reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>
+       <reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>
+       <reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>
+       <reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>
+       <reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>
+       <reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>
+       <reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>
+       <reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>
+       <reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>
+       <reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>
+       <reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>
+       <reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>
+       <reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>
+       <reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>
+       <reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>
+       <reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>
+       <reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>
+       <reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>
+       <reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>
+       <reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>
+       <reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>
+       <reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>
+       <reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>
+       <reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>
+       <reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>
+       <reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>
+       <reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>
+       <reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>
+       <reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>
+       <reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>
+       <reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>
+       <reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>
+       <reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>
+       <reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>
+       <reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>
+       <reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>
+       <reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>
+       <reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>
+       <reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>
+       <reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>
+       <reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>
+       <reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>
+       <reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>
+       <reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>
+       <reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>
+       <reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>
+       <reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>
+       <reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>
+       <reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>
+       <reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>
+       <reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>
+       <reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>
+       <reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>
+       <reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>
+       <reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>
+       <reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>
+       <reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>
+       <reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>
+       <reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>
+       <reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>
+       <reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>
+       <reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>
+       <reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>
+       <reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>
+       <reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>
+       <reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>
+       <reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>
+       <reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>
+       <reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>
+       <reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>
+       <reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>
+
+       <!-- CP registers -->
+       <reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>
+       <reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>
+       <reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>
+       <reg32 offset="0x01cd" name="CP_ROQ_DATA"/>
+       <reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>
+       <reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>
+       <reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>
+       <!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->
+       <reg32 offset="0x01da" name="CP_MEQ_ADDR"/>
+       <reg32 offset="0x01db" name="CP_MEQ_DATA"/>
+       <reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>
+       <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
+
+       <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>
+       <reg32 offset="0x045c" name="CP_HW_FAULT"/>
+       <reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>
+       <reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>
+       <array offset="0x0460" name="CP_PROTECT" stride="1" length="16">
+               <reg32 offset="0x0" name="REG"/>
+       </array>
+       <reg32 offset="0x054d" name="CP_AHB_FAULT"/>
+
+       <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>
+       <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>
+       <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
+
+       <!-- these I guess or either SP or HLSQ since related to shader core setup: -->
+       <reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">
+               <doc>
+                       The pair of MEM_SIZE/ADDR registers get programmed
+                       in sequence with the size/addr of each buffer.
+               </doc>
+       </reg32>
+       <reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>
+
+       <!-- GRAS registers -->
+       <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
+               <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/> <!-- is it more bits? -->
+               <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
+               <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
+               <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
+               <bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>
+               <bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>
+               <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">
+                       <doc>aka clip_halfz</doc>
+               </bitfield>
+               <!-- set when gl_FragCoord.z is enabled in frag shader: -->
+               <bitfield name="ZCOORD" pos="23" type="boolean"/>
+               <bitfield name="WCOORD" pos="24" type="boolean"/>
+               <!-- set when frag shader writes z (so early z test disabled: -->
+               <bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>
+               <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">
+               <bitfield name="HORZ" low="0" high="9" type="uint"/>
+               <bitfield name="VERT" low="10" high="19" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>
+       <reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>
+       <reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>
+       <reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>
+       <reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>
+       <reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>
+       <reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">
+               <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+               <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+       </reg32>
+       <reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
+       <reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">
+               <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
+               <doc>range of -8.0 to 8.0</doc>
+       </reg32>
+       <reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">
+               <doc>range of -512.0 to 512.0</doc>
+       </reg32>
+       <reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">
+               <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+               <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+               <bitfield name="FRONT_CW" pos="2" type="boolean"/>
+               <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
+               <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2072" name="GRAS_SC_CONTROL">
+               <!-- complete wild-ass-guess for sizes of these bitfields.. -->
+               <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
+               <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
+               <bitfield name="RASTER_MODE" low="12" high="15"/>
+       </reg32>
+
+       <reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
+       <reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
+       <reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+       <reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+
+       <!-- RB registers -->
+       <reg32 offset="0x20c0" name="RB_MODE_CONTROL">
+               <!-- guess on the # of bits here.. -->
+               <bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>
+               <doc>
+                       RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS
+               </doc>
+               <bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>
+               <bitfield name="MRT" low="12" high="13" type="uint">
+                       <doc>render targets - 1</doc>
+               </bitfield>
+               <bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>
+               <bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x20c1" name="RB_RENDER_CONTROL">
+               <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
+               <bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>
+               <bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>
+               <!-- set when gl_FrontFacing is accessed in frag shader: -->
+               <bitfield name="FACENESS" pos="3" type="boolean"/>
+               <bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>
+               <bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>
+               <!--
+                       ENABLE_GMEM not set on mem2gmem..  so possibly it is actually
+                       controlling blend or readback from GMEM??
+                -->
+               <bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
+               <bitfield name="XCOORD" pos="14" type="boolean"/>
+               <bitfield name="YCOORD" pos="15" type="boolean"/>
+               <bitfield name="ZCOORD" pos="16" type="boolean"/>
+               <bitfield name="WCOORD" pos="17" type="boolean"/>
+               <bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
+               <bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
+               <bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
+               <bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>
+               <bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>
+               <bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x20c2" name="RB_MSAA_CONTROL">
+               <bitfield name="DISABLE" pos="10" type="boolean"/>
+               <bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>
+               <bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>
+       </reg32>
+       <reg32 offset="0x20c3" name="RB_ALPHA_REF">
+               <bitfield name="UINT" low="8" high="15" type="hex"/>
+               <bitfield name="FLOAT" low="16" high="31" type="float"/>
+       </reg32>
+       <array offset="0x20c4" name="RB_MRT" stride="4" length="4">
+               <reg32 offset="0x0" name="CONTROL">
+                       <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
+                       <!-- both these bits seem to get set when enabling GL_BLEND.. -->
+                       <bitfield name="BLEND" pos="4" type="boolean"/>
+                       <bitfield name="BLEND2" pos="5" type="boolean"/>
+                       <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
+                       <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
+                       <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
+               </reg32>
+               <reg32 offset="0x1" name="BUF_INFO">
+                       <bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>
+                       <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>
+                       <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
+                       <bitfield name="COLOR_SRGB" pos="14" type="boolean"/>
+                       <doc>
+                               Pitch (actually, appears to be pitch in bytes, so really is a stride)
+                               in GMEM, so pitch of the current tile.
+                       </doc>
+                       <bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>
+               </reg32>
+               <reg32 offset="0x2" name="BUF_BASE">
+                       <doc>offset into GMEM (or system memory address in bypass mode)</doc>
+                       <bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>
+               </reg32>
+               <reg32 offset="0x3" name="BLEND_CONTROL">
+                       <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
+                       <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
+                       <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
+                       <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
+                       <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
+                       <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
+                       <bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>
+               </reg32>
+       </array>
+
+       <reg32 offset="0x20e4" name="RB_BLEND_RED">
+               <bitfield name="UINT" low="0" high="7" type="hex"/>
+               <bitfield name="FLOAT" low="16" high="31" type="float"/>
+       </reg32>
+       <reg32 offset="0x20e5" name="RB_BLEND_GREEN">
+               <bitfield name="UINT" low="0" high="7" type="hex"/>
+               <bitfield name="FLOAT" low="16" high="31" type="float"/>
+       </reg32>
+       <reg32 offset="0x20e6" name="RB_BLEND_BLUE">
+               <bitfield name="UINT" low="0" high="7" type="hex"/>
+               <bitfield name="FLOAT" low="16" high="31" type="float"/>
+       </reg32>
+       <reg32 offset="0x20e7" name="RB_BLEND_ALPHA">
+               <bitfield name="UINT" low="0" high="7" type="hex"/>
+               <bitfield name="FLOAT" low="16" high="31" type="float"/>
+       </reg32>
+
+       <reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>
+       <reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>
+       <reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>
+       <reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>
+       <reg32 offset="0x20ec" name="RB_COPY_CONTROL">
+               <!-- not sure # of bits -->
+               <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
+               <bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>
+               <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
+               <bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>
+               <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
+               <bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->
+               <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
+       </reg32>
+       <reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">
+               <bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>
+       </reg32>
+       <reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">
+               <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
+               <!-- not actually sure about max pitch... -->
+               <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
+       </reg32>
+       <reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">
+               <bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>
+               <bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>
+               <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
+               <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
+               <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
+               <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
+       </reg32>
+       <reg32 offset="0x2100" name="RB_DEPTH_CONTROL">
+               <!--
+                       guessing that this matches a2xx with the stencil fields
+                       moved out into RB_STENCIL_CONTROL?
+                -->
+               <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
+               <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
+               <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
+               <bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
+               <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
+               <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
+               <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+               <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
+               <doc>seems to be always set to 0x00000000</doc>
+       </reg32>
+       <reg32 offset="0x2102" name="RB_DEPTH_INFO">
+               <bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>
+               <doc>
+                       DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
+                       bin_w * bin_h / 1024 (possible rounded up to multiple of
+                       something??  ie. 39 becomes 40, 78 becomes 80.. 75 becomes
+                       80.. so maybe it needs to be multiple of 8??
+               </doc>
+               <bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>
+       </reg32>
+       <reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">
+               <doc>
+                       Pitch of depth buffer or combined depth+stencil buffer
+                       in z24s8 cases.
+               </doc>
+       </reg32>
+       <reg32 offset="0x2104" name="RB_STENCIL_CONTROL">
+               <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+               <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
+               <!--
+                       set for stencil operations that require read from stencil
+                       buffer, but not for example for stencil clear (which does
+                       not require read).. so guessing this is analogous to
+                       READ_DEST_ENABLE for color buffer..
+                -->
+               <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
+               <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
+               <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
+               <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
+               <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+               <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+               <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+               <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+               <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+       </reg32>
+       <reg32 offset="0x2105" name="RB_STENCIL_CLEAR">
+               <doc>seems to be always set to 0x00000000</doc>
+       </reg32>
+       <reg32 offset="0x2106" name="RB_STENCIL_INFO">
+               <doc>Base address for stencil when not using interleaved depth/stencil</doc>
+               <bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>
+       </reg32>
+       <reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">
+               <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
+       </reg32>
+       <reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+       <reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+       <!-- VSC == visibility stream c?? -->
+       <reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">
+               <doc>seems to be set to 0x00000002 during binning pass</doc>
+               <bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x210e" name="RB_WINDOW_OFFSET">
+               <doc>X/Y offset of current bin</doc>
+               <bitfield name="X" low="0" high="15" type="uint"/>
+               <bitfield name="Y" low="16" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">
+               <bitfield name="RESET" pos="0" type="boolean"/>
+               <bitfield name="COPY" pos="1" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>
+       <reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>
+       <reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>
+
+       <!-- PC registers -->
+       <reg32 offset="0x21e1" name="VGT_BIN_BASE">
+               <doc>
+                       seems to be where firmware writes BIN_DATA_ADDR from
+                       CP_SET_BIN_DATA packet..  probably should be called
+                       PC_BIN_BASE (just using name from yamato for now)
+               </doc>
+       </reg32>
+       <reg32 offset="0x21e2" name="VGT_BIN_SIZE">
+               <doc>probably should be PC_BIN_SIZE</doc>
+       </reg32>
+       <reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">
+               <doc>SIZE is current pipe width * height (in tiles)</doc>
+               <bitfield name="SIZE" low="16" high="21" type="uint"/>
+               <doc>
+                       N is some sort of slot # between 0..(SIZE-1).  In case
+                       multiple tiles use same pipe, each tile gets unique slot #
+               </doc>
+               <bitfield name="N" low="22" high="26" type="uint"/>
+       </reg32>
+       <reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>
+       <reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">
+               <doc>
+                       STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4
+                       (but, in cases where you'd expect 1, the blob driver uses
+                       2, so possibly 0 (no varying) or minimum of 2)
+               </doc>
+               <bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>
+               <bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
+               <bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
+               <bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>
+               <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
+               <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
+               <!-- PSIZE bit set if gl_PointSize written: -->
+               <bitfield name="PSIZE" pos="26" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>
+
+       <!-- HLSQ registers -->
+       <bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">
+               <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+               <bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>
+               <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
+       </bitset>
+       <bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">
+               <!-- are these a3xx_regid?? -->
+               <bitfield name="STARTENTRY" low="0" high="8"/>
+               <bitfield name="ENDENTRY" low="16" high="24"/>
+       </bitset>
+
+       <reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">
+               <bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>
+               <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
+               <bitfield name="COMPUTEMODE" pos="8" type="boolean"/>
+               <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
+               <bitfield name="RESERVED2" pos="10" type="boolean"/>
+               <bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>
+               <bitfield name="FSONLYTEX" pos="25" type="boolean"/>
+               <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
+               <bitfield name="CONSTMODE" pos="27" type="uint"/>
+               <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
+               <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
+               <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
+               <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">
+               <bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>
+               <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
+               <bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>
+       </reg32>
+       <reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">
+               <bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>
+               <bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>
+               <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
+               <!-- register loaded with position (bary.f, gl_FragCoord, etc) -->
+               <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+       </reg32>
+       <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
+       <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
+       <reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
+       <reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
+       <reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">
+               <bitfield name="WORKDIM" low="0" high="1" type="uint"/>
+               <bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>
+               <bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>
+               <bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>
+       </reg32>
+       <array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">
+               <doc>indexed by dimension</doc>
+               <reg32 offset="0" name="SIZE" type="uint"/>
+               <reg32 offset="1" name="OFFSET" type="uint"/>
+       </array>
+       <reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>
+       <reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>
+       <reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>
+       <array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">
+               <doc>indexed by dimension, global_size / local_size</doc>
+               <reg32 offset="0" name="RATIO" type="uint"/>
+       </array>
+       <reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>
+       <reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>
+       <reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>
+
+       <!-- VFD registers -->
+       <reg32 offset="0x2240" name="VFD_CONTROL_0">
+               <doc>
+                       TOTALATTRTOVS is # of attributes to vertex shader, in register
+                       slots (ie. vec4+vec3 -> 7)
+               </doc>
+               <bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>
+               <bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>
+               <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
+               <bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>
+               <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
+               <bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2241" name="VFD_CONTROL_1">
+               <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
+               <bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>
+               <bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>
+               <bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>
+               <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
+               <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
+       </reg32>
+       <reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>
+       <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
+       <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
+       <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
+       <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
+       <array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
+               <reg32 offset="0x0" name="INSTR_0">
+                       <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
+                       <bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>
+                       <bitfield name="INSTANCED" pos="16" type="boolean"/>
+                       <bitfield name="SWITCHNEXT" pos="17" type="boolean"/>
+                       <bitfield name="INDEXCODE" low="18" high="23" type="uint"/>
+                       <bitfield name="STEPRATE" low="24" high="31" type="uint"/>
+               </reg32>
+               <reg32 offset="0x1" name="INSTR_1"/>
+       </array>
+       <array offset="0x2266" name="VFD_DECODE" stride="1" length="16">
+               <reg32 offset="0x0" name="INSTR">
+                       <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
+                       <!-- not sure if this is a bit flag and another flag above it, or?? -->
+                       <bitfield name="CONSTFILL" pos="4" type="boolean"/>
+                       <bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>
+                       <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
+                       <bitfield name="INT" pos="20" type="boolean"/>
+                       <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
+                       <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
+                       <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
+                       <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
+                       <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
+               </reg32>
+       </array>
+       <reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">
+               <bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>
+               <!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->
+               <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
+       </reg32>
+
+       <!-- VPC registers -->
+       <reg32 offset="0x2280" name="VPC_ATTR">
+               <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
+               <!-- PSIZE bit set if gl_PointSize written: -->
+               <bitfield name="PSIZE" pos="9" type="boolean"/>
+               <bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>
+               <bitfield name="LMSIZE" low="28" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x2281" name="VPC_PACK">
+               <!-- these are always seem to be set to same as TOTALATTR -->
+               <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
+               <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
+       </reg32>
+       <!--
+               varying interpolate mode.  One field per scalar/component
+               (since varying slots are scalar, so things don't have to
+               be aligned to vec4).
+               4 regs * 16 scalar components each => 16 vec4
+        -->
+       <array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">
+               <reg32 offset="0x0" name="MODE">
+                       <bitfield name="C0" low="0"  high="1"  type="a3xx_intp_mode"/>
+                       <bitfield name="C1" low="2"  high="3"  type="a3xx_intp_mode"/>
+                       <bitfield name="C2" low="4"  high="5"  type="a3xx_intp_mode"/>
+                       <bitfield name="C3" low="6"  high="7"  type="a3xx_intp_mode"/>
+                       <bitfield name="C4" low="8"  high="9"  type="a3xx_intp_mode"/>
+                       <bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>
+                       <bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>
+                       <bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>
+                       <bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>
+                       <bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>
+                       <bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>
+                       <bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>
+                       <bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>
+                       <bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>
+                       <bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>
+                       <bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>
+               </reg32>
+       </array>
+       <array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">
+               <reg32 offset="0x0" name="MODE">
+                       <bitfield name="C0" low="0"  high="1"  type="a3xx_repl_mode"/>
+                       <bitfield name="C1" low="2"  high="3"  type="a3xx_repl_mode"/>
+                       <bitfield name="C2" low="4"  high="5"  type="a3xx_repl_mode"/>
+                       <bitfield name="C3" low="6"  high="7"  type="a3xx_repl_mode"/>
+                       <bitfield name="C4" low="8"  high="9"  type="a3xx_repl_mode"/>
+                       <bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>
+                       <bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>
+                       <bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>
+                       <bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>
+                       <bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>
+                       <bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>
+                       <bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>
+                       <bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>
+                       <bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>
+                       <bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>
+                       <bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>
+               </reg32>
+       </array>
+       <reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>
+       <reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>
+
+       <!-- SP registers -->
+       <bitset name="a3xx_vs_fs_length_reg" inline="yes">
+               <bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>
+       </bitset>
+
+       <bitset name="sp_vs_fs_obj_offset_reg" inline="yes">
+               <bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>
+               <doc>
+                       From register spec:
+                       SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
+                       start offset in on chip RAM,
+                       128bit aligned
+               </doc>
+               <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+               <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+       </bitset>
+
+       <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
+               <!-- this bit is set during resolve pass: -->
+               <bitfield name="RESOLVE" pos="16" type="boolean"/>
+               <bitfield name="CONSTMODE" pos="18" type="uint"/>
+               <bitfield name="BINNING" pos="19" type="boolean"/>
+               <bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>
+               <!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->
+               <bitfield name="L0MODE" low="22" high="23" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">
+               <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+               <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
+               <!-- maybe CACHEINVALID is two bits?? -->
+               <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
+               <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
+               <doc>
+                       The full/half register footprint is in units of four components,
+                       so if r0.x is used, that counts as all of r0.[xyzw] as used.
+                       There are separate full/half register footprint values as the
+                       full and half registers are independent (not overlapping).
+                       Presumably the thread scheduler hardware allocates the full/half
+                       register names from the actual physical register file and
+                       handles the register renaming.
+               </doc>
+               <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+               <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+               <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
+               <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
+               <doc>
+                       From regspec:
+                       SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
+                       If bit31 is 1, it means overflow
+                       or any long shader.
+               </doc>
+               <bitfield name="LENGTH" low="24" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
+               <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+               <!--
+                       not sure about full vs half const.. I can't get blob generate
+                       something with a mediump/lowp uniform.
+                -->
+               <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
+               <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
+               <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
+               <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
+               <bitfield name="POS2DMODE" pos="16" type="boolean"/>
+               <bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>
+       </reg32>
+       <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">
+               <reg32 offset="0x0" name="REG">
+                       <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+                       <bitfield name="A_HALF" pos="8" type="boolean"/>
+                       <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
+                       <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+                       <bitfield name="B_HALF" pos="24" type="boolean"/>
+                       <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
+               </reg32>
+       </array>
+       <array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">
+               <reg32 offset="0x0" name="REG">
+                       <doc>
+                               These seem to be offsets for storage of the varyings.
+                               Always seems to start from 8, possibly loc 0 and 4
+                               are for gl_Position and gl_PointSize?
+                       </doc>
+                       <bitfield name="OUTLOC0" low="0" high="6" type="uint"/>
+                       <bitfield name="OUTLOC1" low="8" high="14" type="uint"/>
+                       <bitfield name="OUTLOC2" low="16" high="22" type="uint"/>
+                       <bitfield name="OUTLOC3" low="24" high="30" type="uint"/>
+               </reg32>
+       </array>
+       <reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
+       <doc>
+               SP_VS_OBJ_START_REG contains pointer to the vertex shader program,
+               immediately followed by the binning shader program (although I
+               guess that is probably just re-using the same gpu buffer)
+       </doc>
+       <reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>
+       <reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">
+               <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
+               <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
+               <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">
+               <bitfield name="BURSTLEN" low="0" high="4"/>
+               <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
+       </reg32>
+       <reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>
+       <reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
+       <reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">
+               <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+               <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
+               <!-- maybe CACHEINVALID is two bits?? -->
+               <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
+               <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
+               <doc>
+                       The full/half register footprint is in units of four components,
+                       so if r0.x is used, that counts as all of r0.[xyzw] as used.
+                       There are separate full/half register footprint values as the
+                       full and half registers are independent (not overlapping).
+                       Presumably the thread scheduler hardware allocates the full/half
+                       register names from the actual physical register file and
+                       handles the register renaming.
+               </doc>
+               <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+               <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+               <bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>
+               <bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>
+               <bitfield name="OUTORDERED" pos="19" type="boolean"/>
+               <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
+               <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
+               <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
+               <bitfield name="COMPUTEMODE" pos="23" type="boolean"/>
+               <doc>
+                       From regspec:
+                       SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
+                       If bit31 is 1, it means overflow
+                       or any long shader.
+               </doc>
+               <bitfield name="LENGTH" low="24" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
+               <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+               <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
+               <bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
+               <bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
+       <doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>
+       <reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>
+       <reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">
+               <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
+               <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
+               <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
+       </reg32>
+       <reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">
+               <bitfield name="BURSTLEN" low="0" high="4"/>
+               <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
+       </reg32>
+       <reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>
+       <reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">
+               <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
+       </reg32>
+       <reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">
+               <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
+       </reg32>
+       <reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">
+               <bitfield name="MRT" low="0" high="1" type="uint">
+                       <doc>render targets - 1</doc>
+               </bitfield>
+               <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
+               <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
+       </reg32>
+       <array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">
+               <reg32 offset="0x0" name="REG">
+                       <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+                       <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+                       <bitfield name="SINT" pos="10" type="boolean"/>
+                       <bitfield name="UINT" pos="11" type="boolean"/>
+               </reg32>
+       </array>
+       <array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">
+               <reg32 offset="0x0" name="REG">
+                       <bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>
+               </reg32>
+       </array>
+       <reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
+
+       <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>
+       <!-- TPL1 registers -->
+       <!-- assume VS/FS_TEX_OFFSET is same -->
+       <bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">
+               <bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>
+               <bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>
+               <!-- not sure the size of this: -->
+               <bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>
+       </bitset>
+       <reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
+       <reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
+       <reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
+       <reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
+
+       <!-- VBIF registers -->
+       <reg32 offset="0x3001" name="VBIF_CLKON"/>
+       <reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>
+       <reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>
+       <reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>
+       <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
+       <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
+       <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
+       <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
+       <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
+       <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
+       <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
+       <reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>
+       <reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>
+       <reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>
+       <reg32 offset="0x303c" name="VBIF_ARB_CTL"/>
+       <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
+       <reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>
+       <reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>
+       <reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>
+
+       <bitset name="a3xx_vbif_perf_cnt" inline="yes">
+               <bitfield name="CNT0" pos="0" type="boolean"/>
+               <bitfield name="CNT1" pos="1" type="boolean"/>
+               <bitfield name="PWRCNT0" pos="2" type="boolean"/>
+               <bitfield name="PWRCNT1" pos="3" type="boolean"/>
+               <bitfield name="PWRCNT2" pos="4" type="boolean"/>
+       </bitset>
+
+       <reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>
+       <reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>
+       <reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>
+       <reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>
+       <reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>
+       <reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>
+       <reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>
+       <reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>
+       <reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>
+       <reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>
+       <reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>
+       <reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>
+       <reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>
+
+
+       <reg32 offset="0x0c01" name="VSC_BIN_SIZE">
+               <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
+               <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
+       </reg32>
+
+       <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>
+       <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
+               <reg32 offset="0x0" name="CONFIG">
+                       <doc>
+                               Configures the mapping between VSC_PIPE buffer and
+                               bin, X/Y specify the bin index in the horiz/vert
+                               direction (0,0 is upper left, 0,1 is leftmost bin
+                               on second row, and so on).  W/H specify the number
+                               of bins assigned to this VSC_PIPE in the horiz/vert
+                               dimension.
+                       </doc>
+                       <bitfield name="X" low="0" high="9" type="uint"/>
+                       <bitfield name="Y" low="10" high="19" type="uint"/>
+                       <bitfield name="W" low="20" high="23" type="uint"/>
+                       <bitfield name="H" low="24" high="27" type="uint"/>
+               </reg32>
+               <reg32 offset="0x1" name="DATA_ADDRESS"/>
+               <reg32 offset="0x2" name="DATA_LENGTH"/>
+       </array>
+       <reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">
+               <doc>seems to be set to 0x00000001 during binning pass</doc>
+               <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0c3d" name="UNKNOWN_0C3D">
+               <doc>seems to be always set to 0x00000001</doc>
+       </reg32>
+       <reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>
+       <reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>
+       <reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>
+       <reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>
+       <reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">
+               <doc>seems to be always set to 0x00000001</doc>
+       </reg32>
+
+       <reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
+       <reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
+       <reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
+       <reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
+       <array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">
+               <reg32 offset="0x0" name="X"/>
+               <reg32 offset="0x1" name="Y"/>
+               <reg32 offset="0x2" name="Z"/>
+               <reg32 offset="0x3" name="W"/>
+       </array>
+       <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
+       <reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>
+       <reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>
+       <reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>
+       <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
+               <bitfield name="WIDTH" low="0" high="13" type="uint"/>
+               <bitfield name="HEIGHT" low="14" high="27" type="uint"/>
+       </reg32>
+       <reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+       <reg32 offset="0x0e43" name="UNKNOWN_0E43">
+               <doc>seems to be always set to 0x00000001</doc>
+       </reg32>
+       <reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>
+       <reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>
+       <reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>
+       <reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>
+       <reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>
+       <reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>
+       <reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>
+       <reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>
+       <reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">
+               <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
+               <bitfield name="ADDR" low="0" high="27" type="hex"/>
+       </reg32>
+       <reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">
+               <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
+               <bitfield name="ADDR" low="0" high="27" type="hex"/>
+               <!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->
+               <bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>
+               <bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>
+       <reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>
+       <reg32 offset="0x0ee0" name="UNKNOWN_0EE0">
+               <doc>seems to be always set to 0x00000003</doc>
+       </reg32>
+       <reg32 offset="0x0f03" name="UNKNOWN_0F03">
+               <doc>seems to be always set to 0x00000001</doc>
+       </reg32>
+       <reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>
+       <reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>
+       <reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>
+       <reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>
+       <reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>
+       <reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>
+
+       <!-- this seems to be the register that CP_RUN_OPENCL writes: -->
+       <reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>
+
+       <!-- seems to be same as a2xx according to fwdump.. -->
+       <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
+       <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
+       <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
+</domain>
+
+<domain name="A3XX_TEX_SAMP" width="32">
+       <doc>Texture sampler dwords</doc>
+       <enum name="a3xx_tex_filter">
+               <value name="A3XX_TEX_NEAREST" value="0"/>
+               <value name="A3XX_TEX_LINEAR" value="1"/>
+               <value name="A3XX_TEX_ANISO" value="2"/>
+       </enum>
+       <enum name="a3xx_tex_clamp">
+               <value name="A3XX_TEX_REPEAT" value="0"/>
+               <value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>
+               <value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>
+               <value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>
+               <value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>
+       </enum>
+       <enum name="a3xx_tex_aniso">
+               <value name="A3XX_TEX_ANISO_1" value="0"/>
+               <value name="A3XX_TEX_ANISO_2" value="1"/>
+               <value name="A3XX_TEX_ANISO_4" value="2"/>
+               <value name="A3XX_TEX_ANISO_8" value="3"/>
+               <value name="A3XX_TEX_ANISO_16" value="4"/>
+       </enum>
+       <reg32 offset="0" name="0">
+               <bitfield name="CLAMPENABLE" pos="0" type="boolean"/>
+               <bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>
+               <bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>
+               <bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>
+               <bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>
+               <bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>
+               <bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>
+               <bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>
+               <bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>
+               <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>
+               <!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->
+               <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
+       </reg32>
+       <reg32 offset="1" name="1">
+               <bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>
+               <bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>
+               <bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>
+       </reg32>
+</domain>
+
+<domain name="A3XX_TEX_CONST" width="32">
+       <doc>Texture constant dwords</doc>
+       <enum name="a3xx_tex_swiz">
+               <!-- same as a2xx? -->
+               <value name="A3XX_TEX_X" value="0"/>
+               <value name="A3XX_TEX_Y" value="1"/>
+               <value name="A3XX_TEX_Z" value="2"/>
+               <value name="A3XX_TEX_W" value="3"/>
+               <value name="A3XX_TEX_ZERO" value="4"/>
+               <value name="A3XX_TEX_ONE" value="5"/>
+       </enum>
+       <enum name="a3xx_tex_type">
+               <value name="A3XX_TEX_1D" value="0"/>
+               <value name="A3XX_TEX_2D" value="1"/>
+               <value name="A3XX_TEX_CUBE" value="2"/>
+               <value name="A3XX_TEX_3D" value="3"/>
+       </enum>
+       <enum name="a3xx_tex_msaa">
+               <value name="A3XX_TPL1_MSAA1X" value="0"/>
+               <value name="A3XX_TPL1_MSAA2X" value="1"/>
+               <value name="A3XX_TPL1_MSAA4X" value="2"/>
+               <value name="A3XX_TPL1_MSAA8X" value="3"/>
+       </enum>
+       <reg32 offset="0" name="0">
+               <bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>
+               <bitfield name="SRGB" pos="2" type="boolean"/>
+               <bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>
+               <bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>
+               <bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>
+               <bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>
+               <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
+               <bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>
+               <bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>
+               <bitfield name="NOCONVERT" pos="29" type="boolean"/>
+               <bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>
+       </reg32>
+       <reg32 offset="1" name="1">
+               <bitfield name="HEIGHT" low="0" high="13" type="uint"/>
+               <bitfield name="WIDTH" low="14" high="27" type="uint"/>
+               <bitfield name="FETCHSIZE" low="28" high="31" type="a3xx_tex_fetchsize"/>
+       </reg32>
+       <reg32 offset="2" name="2">
+               <doc>INDX is index of texture address(es) in MIPMAP state block</doc>
+               <bitfield name="INDX" low="0" high="8" type="uint"/>
+               <doc>Pitch in bytes (so actually stride)</doc>
+               <bitfield name="PITCH" low="12" high="29" type="uint"/>
+               <doc>SWAP bit is set for BGRA instead of RGBA</doc>
+               <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
+       </reg32>
+       <reg32 offset="3" name="3">
+               <!--
+               Update: the two LAYERSZn seem not to be the same thing.
+               According to Ilia's experimentation the first one goes up
+               to at *least* bit 14..
+                -->
+               <bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>
+               <bitfield name="DEPTH" low="17" high="27" type="uint"/>
+               <bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>
+       </reg32>
+</domain>
+
+</database>
diff --git a/src/freedreno/registers/a3xx.xml.h b/src/freedreno/registers/a3xx.xml.h
deleted file mode 100644 (file)
index 70cc5ea..0000000
+++ /dev/null
@@ -1,3246 +0,0 @@
-#ifndef A3XX_XML
-#define A3XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-01-21 14:36:17)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43561 bytes, from 2019-06-10 13:39:33)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  84030 bytes, from 2019-07-01 13:05:23)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147548 bytes, from 2019-06-10 13:39:33)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 152605 bytes, from 2019-07-01 13:13:03)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
-
-Copyright (C) 2013-2019 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum a3xx_tile_mode {
-       LINEAR = 0,
-       TILE_4X4 = 1,
-       TILE_32X32 = 2,
-       TILE_4X2 = 3,
-};
-
-enum a3xx_state_block_id {
-       HLSQ_BLOCK_ID_TP_TEX = 2,
-       HLSQ_BLOCK_ID_TP_MIPMAP = 3,
-       HLSQ_BLOCK_ID_SP_VS = 4,
-       HLSQ_BLOCK_ID_SP_FS = 6,
-};
-
-enum a3xx_cache_opcode {
-       INVALIDATE = 1,
-};
-
-enum a3xx_vtx_fmt {
-       VFMT_32_FLOAT = 0,
-       VFMT_32_32_FLOAT = 1,
-       VFMT_32_32_32_FLOAT = 2,
-       VFMT_32_32_32_32_FLOAT = 3,
-       VFMT_16_FLOAT = 4,
-       VFMT_16_16_FLOAT = 5,
-       VFMT_16_16_16_FLOAT = 6,
-       VFMT_16_16_16_16_FLOAT = 7,
-       VFMT_32_FIXED = 8,
-       VFMT_32_32_FIXED = 9,
-       VFMT_32_32_32_FIXED = 10,
-       VFMT_32_32_32_32_FIXED = 11,
-       VFMT_16_SINT = 16,
-       VFMT_16_16_SINT = 17,
-       VFMT_16_16_16_SINT = 18,
-       VFMT_16_16_16_16_SINT = 19,
-       VFMT_16_UINT = 20,
-       VFMT_16_16_UINT = 21,
-       VFMT_16_16_16_UINT = 22,
-       VFMT_16_16_16_16_UINT = 23,
-       VFMT_16_SNORM = 24,
-       VFMT_16_16_SNORM = 25,
-       VFMT_16_16_16_SNORM = 26,
-       VFMT_16_16_16_16_SNORM = 27,
-       VFMT_16_UNORM = 28,
-       VFMT_16_16_UNORM = 29,
-       VFMT_16_16_16_UNORM = 30,
-       VFMT_16_16_16_16_UNORM = 31,
-       VFMT_32_UINT = 32,
-       VFMT_32_32_UINT = 33,
-       VFMT_32_32_32_UINT = 34,
-       VFMT_32_32_32_32_UINT = 35,
-       VFMT_32_SINT = 36,
-       VFMT_32_32_SINT = 37,
-       VFMT_32_32_32_SINT = 38,
-       VFMT_32_32_32_32_SINT = 39,
-       VFMT_8_UINT = 40,
-       VFMT_8_8_UINT = 41,
-       VFMT_8_8_8_UINT = 42,
-       VFMT_8_8_8_8_UINT = 43,
-       VFMT_8_UNORM = 44,
-       VFMT_8_8_UNORM = 45,
-       VFMT_8_8_8_UNORM = 46,
-       VFMT_8_8_8_8_UNORM = 47,
-       VFMT_8_SINT = 48,
-       VFMT_8_8_SINT = 49,
-       VFMT_8_8_8_SINT = 50,
-       VFMT_8_8_8_8_SINT = 51,
-       VFMT_8_SNORM = 52,
-       VFMT_8_8_SNORM = 53,
-       VFMT_8_8_8_SNORM = 54,
-       VFMT_8_8_8_8_SNORM = 55,
-       VFMT_10_10_10_2_UINT = 56,
-       VFMT_10_10_10_2_UNORM = 57,
-       VFMT_10_10_10_2_SINT = 58,
-       VFMT_10_10_10_2_SNORM = 59,
-       VFMT_2_10_10_10_UINT = 60,
-       VFMT_2_10_10_10_UNORM = 61,
-       VFMT_2_10_10_10_SINT = 62,
-       VFMT_2_10_10_10_SNORM = 63,
-};
-
-enum a3xx_tex_fmt {
-       TFMT_5_6_5_UNORM = 4,
-       TFMT_5_5_5_1_UNORM = 5,
-       TFMT_4_4_4_4_UNORM = 7,
-       TFMT_Z16_UNORM = 9,
-       TFMT_X8Z24_UNORM = 10,
-       TFMT_Z32_FLOAT = 11,
-       TFMT_UV_64X32 = 16,
-       TFMT_VU_64X32 = 17,
-       TFMT_Y_64X32 = 18,
-       TFMT_NV12_64X32 = 19,
-       TFMT_UV_LINEAR = 20,
-       TFMT_VU_LINEAR = 21,
-       TFMT_Y_LINEAR = 22,
-       TFMT_NV12_LINEAR = 23,
-       TFMT_I420_Y = 24,
-       TFMT_I420_U = 26,
-       TFMT_I420_V = 27,
-       TFMT_ATC_RGB = 32,
-       TFMT_ATC_RGBA_EXPLICIT = 33,
-       TFMT_ETC1 = 34,
-       TFMT_ATC_RGBA_INTERPOLATED = 35,
-       TFMT_DXT1 = 36,
-       TFMT_DXT3 = 37,
-       TFMT_DXT5 = 38,
-       TFMT_2_10_10_10_UNORM = 40,
-       TFMT_10_10_10_2_UNORM = 41,
-       TFMT_9_9_9_E5_FLOAT = 42,
-       TFMT_11_11_10_FLOAT = 43,
-       TFMT_A8_UNORM = 44,
-       TFMT_L8_UNORM = 45,
-       TFMT_L8_A8_UNORM = 47,
-       TFMT_8_UNORM = 48,
-       TFMT_8_8_UNORM = 49,
-       TFMT_8_8_8_UNORM = 50,
-       TFMT_8_8_8_8_UNORM = 51,
-       TFMT_8_SNORM = 52,
-       TFMT_8_8_SNORM = 53,
-       TFMT_8_8_8_SNORM = 54,
-       TFMT_8_8_8_8_SNORM = 55,
-       TFMT_8_UINT = 56,
-       TFMT_8_8_UINT = 57,
-       TFMT_8_8_8_UINT = 58,
-       TFMT_8_8_8_8_UINT = 59,
-       TFMT_8_SINT = 60,
-       TFMT_8_8_SINT = 61,
-       TFMT_8_8_8_SINT = 62,
-       TFMT_8_8_8_8_SINT = 63,
-       TFMT_16_FLOAT = 64,
-       TFMT_16_16_FLOAT = 65,
-       TFMT_16_16_16_16_FLOAT = 67,
-       TFMT_16_UINT = 68,
-       TFMT_16_16_UINT = 69,
-       TFMT_16_16_16_16_UINT = 71,
-       TFMT_16_SINT = 72,
-       TFMT_16_16_SINT = 73,
-       TFMT_16_16_16_16_SINT = 75,
-       TFMT_16_UNORM = 76,
-       TFMT_16_16_UNORM = 77,
-       TFMT_16_16_16_16_UNORM = 79,
-       TFMT_16_SNORM = 80,
-       TFMT_16_16_SNORM = 81,
-       TFMT_16_16_16_16_SNORM = 83,
-       TFMT_32_FLOAT = 84,
-       TFMT_32_32_FLOAT = 85,
-       TFMT_32_32_32_32_FLOAT = 87,
-       TFMT_32_UINT = 88,
-       TFMT_32_32_UINT = 89,
-       TFMT_32_32_32_32_UINT = 91,
-       TFMT_32_SINT = 92,
-       TFMT_32_32_SINT = 93,
-       TFMT_32_32_32_32_SINT = 95,
-       TFMT_2_10_10_10_UINT = 96,
-       TFMT_10_10_10_2_UINT = 97,
-       TFMT_ETC2_RG11_SNORM = 112,
-       TFMT_ETC2_RG11_UNORM = 113,
-       TFMT_ETC2_R11_SNORM = 114,
-       TFMT_ETC2_R11_UNORM = 115,
-       TFMT_ETC2_RGBA8 = 116,
-       TFMT_ETC2_RGB8A1 = 117,
-       TFMT_ETC2_RGB8 = 118,
-};
-
-enum a3xx_tex_fetchsize {
-       TFETCH_DISABLE = 0,
-       TFETCH_1_BYTE = 1,
-       TFETCH_2_BYTE = 2,
-       TFETCH_4_BYTE = 3,
-       TFETCH_8_BYTE = 4,
-       TFETCH_16_BYTE = 5,
-};
-
-enum a3xx_color_fmt {
-       RB_R5G6B5_UNORM = 0,
-       RB_R5G5B5A1_UNORM = 1,
-       RB_R4G4B4A4_UNORM = 3,
-       RB_R8G8B8_UNORM = 4,
-       RB_R8G8B8A8_UNORM = 8,
-       RB_R8G8B8A8_SNORM = 9,
-       RB_R8G8B8A8_UINT = 10,
-       RB_R8G8B8A8_SINT = 11,
-       RB_R8G8_UNORM = 12,
-       RB_R8G8_SNORM = 13,
-       RB_R8_UINT = 14,
-       RB_R8_SINT = 15,
-       RB_R10G10B10A2_UNORM = 16,
-       RB_A2R10G10B10_UNORM = 17,
-       RB_R10G10B10A2_UINT = 18,
-       RB_A2R10G10B10_UINT = 19,
-       RB_A8_UNORM = 20,
-       RB_R8_UNORM = 21,
-       RB_R16_FLOAT = 24,
-       RB_R16G16_FLOAT = 25,
-       RB_R16G16B16A16_FLOAT = 27,
-       RB_R11G11B10_FLOAT = 28,
-       RB_R16_SNORM = 32,
-       RB_R16G16_SNORM = 33,
-       RB_R16G16B16A16_SNORM = 35,
-       RB_R16_UNORM = 36,
-       RB_R16G16_UNORM = 37,
-       RB_R16G16B16A16_UNORM = 39,
-       RB_R16_SINT = 40,
-       RB_R16G16_SINT = 41,
-       RB_R16G16B16A16_SINT = 43,
-       RB_R16_UINT = 44,
-       RB_R16G16_UINT = 45,
-       RB_R16G16B16A16_UINT = 47,
-       RB_R32_FLOAT = 48,
-       RB_R32G32_FLOAT = 49,
-       RB_R32G32B32A32_FLOAT = 51,
-       RB_R32_SINT = 52,
-       RB_R32G32_SINT = 53,
-       RB_R32G32B32A32_SINT = 55,
-       RB_R32_UINT = 56,
-       RB_R32G32_UINT = 57,
-       RB_R32G32B32A32_UINT = 59,
-};
-
-enum a3xx_cp_perfcounter_select {
-       CP_ALWAYS_COUNT = 0,
-       CP_AHB_PFPTRANS_WAIT = 3,
-       CP_AHB_NRTTRANS_WAIT = 6,
-       CP_CSF_NRT_READ_WAIT = 8,
-       CP_CSF_I1_FIFO_FULL = 9,
-       CP_CSF_I2_FIFO_FULL = 10,
-       CP_CSF_ST_FIFO_FULL = 11,
-       CP_RESERVED_12 = 12,
-       CP_CSF_RING_ROQ_FULL = 13,
-       CP_CSF_I1_ROQ_FULL = 14,
-       CP_CSF_I2_ROQ_FULL = 15,
-       CP_CSF_ST_ROQ_FULL = 16,
-       CP_RESERVED_17 = 17,
-       CP_MIU_TAG_MEM_FULL = 18,
-       CP_MIU_NRT_WRITE_STALLED = 22,
-       CP_MIU_NRT_READ_STALLED = 23,
-       CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
-       CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
-       CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
-       CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
-       CP_ME_MICRO_RB_STARVED = 30,
-       CP_AHB_RBBM_DWORD_SENT = 40,
-       CP_ME_BUSY_CLOCKS = 41,
-       CP_ME_WAIT_CONTEXT_AVAIL = 42,
-       CP_PFP_TYPE0_PACKET = 43,
-       CP_PFP_TYPE3_PACKET = 44,
-       CP_CSF_RB_WPTR_NEQ_RPTR = 45,
-       CP_CSF_I1_SIZE_NEQ_ZERO = 46,
-       CP_CSF_I2_SIZE_NEQ_ZERO = 47,
-       CP_CSF_RBI1I2_FETCHING = 48,
-};
-
-enum a3xx_gras_tse_perfcounter_select {
-       GRAS_TSEPERF_INPUT_PRIM = 0,
-       GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
-       GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
-       GRAS_TSEPERF_CLIPPED_PRIM = 3,
-       GRAS_TSEPERF_NEW_PRIM = 4,
-       GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
-       GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
-       GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
-       GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
-       GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
-       GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
-       GRAS_TSEPERF_POST_CLIP_PRIM = 11,
-       GRAS_TSEPERF_WORKING_CYCLES = 12,
-       GRAS_TSEPERF_PC_STARVE = 13,
-       GRAS_TSERASPERF_STALL = 14,
-};
-
-enum a3xx_gras_ras_perfcounter_select {
-       GRAS_RASPERF_16X16_TILES = 0,
-       GRAS_RASPERF_8X8_TILES = 1,
-       GRAS_RASPERF_4X4_TILES = 2,
-       GRAS_RASPERF_WORKING_CYCLES = 3,
-       GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
-       GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
-       GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
-};
-
-enum a3xx_hlsq_perfcounter_select {
-       HLSQ_PERF_SP_VS_CONSTANT = 0,
-       HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
-       HLSQ_PERF_SP_FS_CONSTANT = 2,
-       HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
-       HLSQ_PERF_TP_STATE = 4,
-       HLSQ_PERF_QUADS = 5,
-       HLSQ_PERF_PIXELS = 6,
-       HLSQ_PERF_VERTICES = 7,
-       HLSQ_PERF_FS8_THREADS = 8,
-       HLSQ_PERF_FS16_THREADS = 9,
-       HLSQ_PERF_FS32_THREADS = 10,
-       HLSQ_PERF_VS8_THREADS = 11,
-       HLSQ_PERF_VS16_THREADS = 12,
-       HLSQ_PERF_SP_VS_DATA_BYTES = 13,
-       HLSQ_PERF_SP_FS_DATA_BYTES = 14,
-       HLSQ_PERF_ACTIVE_CYCLES = 15,
-       HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
-       HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
-       HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
-       HLSQ_PERF_STALL_CYCLES_UCHE = 19,
-       HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
-       HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
-       HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
-       HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
-       HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
-       HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
-       HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
-       HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
-       HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
-};
-
-enum a3xx_pc_perfcounter_select {
-       PC_PCPERF_VISIBILITY_STREAMS = 0,
-       PC_PCPERF_TOTAL_INSTANCES = 1,
-       PC_PCPERF_PRIMITIVES_PC_VPC = 2,
-       PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
-       PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
-       PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
-       PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
-       PC_PCPERF_VERTICES_TO_VFD = 7,
-       PC_PCPERF_REUSED_VERTICES = 8,
-       PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
-       PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
-       PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
-       PC_PCPERF_CYCLES_IS_WORKING = 12,
-};
-
-enum a3xx_rb_perfcounter_select {
-       RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
-       RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
-       RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
-       RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
-       RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
-       RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
-       RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
-       RB_RBPERF_RB_MARB_DATA = 7,
-       RB_RBPERF_SP_RB_QUAD = 8,
-       RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
-       RB_RBPERF_GMEM_CH0_READ = 10,
-       RB_RBPERF_GMEM_CH1_READ = 11,
-       RB_RBPERF_GMEM_CH0_WRITE = 12,
-       RB_RBPERF_GMEM_CH1_WRITE = 13,
-       RB_RBPERF_CP_CONTEXT_DONE = 14,
-       RB_RBPERF_CP_CACHE_FLUSH = 15,
-       RB_RBPERF_CP_ZPASS_DONE = 16,
-};
-
-enum a3xx_rbbm_perfcounter_select {
-       RBBM_ALAWYS_ON = 0,
-       RBBM_VBIF_BUSY = 1,
-       RBBM_TSE_BUSY = 2,
-       RBBM_RAS_BUSY = 3,
-       RBBM_PC_DCALL_BUSY = 4,
-       RBBM_PC_VSD_BUSY = 5,
-       RBBM_VFD_BUSY = 6,
-       RBBM_VPC_BUSY = 7,
-       RBBM_UCHE_BUSY = 8,
-       RBBM_VSC_BUSY = 9,
-       RBBM_HLSQ_BUSY = 10,
-       RBBM_ANY_RB_BUSY = 11,
-       RBBM_ANY_TEX_BUSY = 12,
-       RBBM_ANY_USP_BUSY = 13,
-       RBBM_ANY_MARB_BUSY = 14,
-       RBBM_ANY_ARB_BUSY = 15,
-       RBBM_AHB_STATUS_BUSY = 16,
-       RBBM_AHB_STATUS_STALLED = 17,
-       RBBM_AHB_STATUS_TXFR = 18,
-       RBBM_AHB_STATUS_TXFR_SPLIT = 19,
-       RBBM_AHB_STATUS_TXFR_ERROR = 20,
-       RBBM_AHB_STATUS_LONG_STALL = 21,
-       RBBM_RBBM_STATUS_MASKED = 22,
-};
-
-enum a3xx_sp_perfcounter_select {
-       SP_LM_LOAD_INSTRUCTIONS = 0,
-       SP_LM_STORE_INSTRUCTIONS = 1,
-       SP_LM_ATOMICS = 2,
-       SP_UCHE_LOAD_INSTRUCTIONS = 3,
-       SP_UCHE_STORE_INSTRUCTIONS = 4,
-       SP_UCHE_ATOMICS = 5,
-       SP_VS_TEX_INSTRUCTIONS = 6,
-       SP_VS_CFLOW_INSTRUCTIONS = 7,
-     &nbs