radv/gfx10: implement a bug workaround for GE_PC_ALLOC

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5c913f29a5a01a063b7a700a94a447b010cba602..4d4f86a7e24ab545bf8f44003b521ea032030977 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3456,18 +3456,6 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
 }
 
-static void
-gfx10_set_ge_pc_alloc(struct radeon_cmdbuf *ctx_cs,
-                     struct radv_pipeline *pipeline,
-                     bool culling)
-{
-       struct radeon_info *info = &pipeline->device->physical_device->rad_info;
-
-       radeon_set_uconfig_reg(ctx_cs, R_030980_GE_PC_ALLOC,
-                              S_030980_OVERSUB_EN(1) |
-                              S_030980_NUM_PC_LINES((culling ? 256 : 128) * info->max_se - 1));
-}
-
 static void
 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
                             struct radeon_cmdbuf *cs,
@@ -3534,9 +3522,6 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
        if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
                radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
                                       outinfo->writes_viewport_index);
-
-       if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
-               gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
 }
 
 static void
@@ -3699,8 +3684,6 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
                               S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
                               S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
                               S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
-
-       gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
 }
 
 static void

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 18b2236e54b0e9ad648f23c276e3a3f3578a9bfc..3d6c672dd0f9254fe6b30d08bf2a95ce97e27b41 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -382,6 +382,19 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                                  S_00B0C0_SOFT_GROUPING_EN(1) |
                                  S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
                radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
+
+               if (physical_device->rad_info.family == CHIP_NAVI10 ||
+                   physical_device->rad_info.family == CHIP_NAVI12 ||
+                   physical_device->rad_info.family == CHIP_NAVI14) {
+                       /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
+                       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+                       radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
+               }
+
+               /* TODO: For culling, replace 128 with 256. */
+               radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
+                                      S_030980_OVERSUB_EN(1) |
+                                      S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
        }
 
        if (physical_device->rad_info.chip_class >= GFX8) {