radeonsi: correct WRITE_DATA.DST_SEL definitions

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 12e80df48842284b6024db990f96fe7f0e85e835..5c8eee0124d8e5d84460c8d240b6fbaa237ab73d 100644 (file)
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -133,11 +133,11 @@
 #define     S_370_WR_ONE_ADDR(x)               (((unsigned)(x) & 0x1) << 16)
 #define     S_370_DST_SEL(x)                   (((unsigned)(x) & 0xf) << 8)
 #define       V_370_MEM_MAPPED_REGISTER                0
-#define       V_370_MEMORY_SYNC                        1
+#define       V_370_MEM_GRBM                   1 /* sync across GRBM */
 #define       V_370_TC_L2                      2
 #define       V_370_GDS                                3
 #define       V_370_RESERVED                   4
-#define       V_370_MEM_ASYNC                  5
+#define       V_370_MEM                                5 /* not on SI */
 #define   R_371_DST_ADDR_LO                    0x371
 #define   R_372_DST_ADDR_HI                    0x372
 #define PKT3_DRAW_INDEX_INDIRECT_MULTI         0x38

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 05e2e600e13320d7d97a19b6ad855be8d257766e..193bf1da5c50babb510f2d1601309b861a9959da 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -453,7 +453,7 @@ radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
        radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                    S_370_WR_CONFIRM(1) |
                    S_370_ENGINE_SEL(V_370_ME));
        radeon_emit(cs, va);
@@ -1262,7 +1262,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
                ++reg_count;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                        S_370_WR_CONFIRM(1) |
                        S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cs, va);
@@ -1286,7 +1286,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
        va += image->offset + image->tc_compat_zrange_offset;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                        S_370_WR_CONFIRM(1) |
                        S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cs, va);
@@ -1399,7 +1399,7 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
        assert(radv_image_has_dcc(image));
 
        radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
-       radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
                                    S_370_WR_CONFIRM(1) |
                                    S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cmd_buffer->cs, va);
@@ -1422,7 +1422,7 @@ radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
        assert(radv_image_has_dcc(image));
 
        radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
-       radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
                                    S_370_WR_CONFIRM(1) |
                                    S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cmd_buffer->cs, va);
@@ -1480,7 +1480,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
        assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+       radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                        S_370_WR_CONFIRM(1) |
                        S_370_ENGINE_SEL(V_370_PFP));
        radeon_emit(cs, va);
@@ -4758,7 +4758,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
        if (!(stageMask & ~top_of_pipe_flags)) {
                /* Just need to sync the PFP engine. */
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+               radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                                S_370_WR_CONFIRM(1) |
                                S_370_ENGINE_SEL(V_370_PFP));
                radeon_emit(cs, va);
@@ -4767,7 +4767,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
        } else if (!(stageMask & ~post_index_fetch_flags)) {
                /* Sync ME because PFP reads index and indirect buffers. */
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+               radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                                S_370_WR_CONFIRM(1) |
                                S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cs, va);

diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index 76854d7bbad1617113f4164b0d8d01305a7f8a1c..ab70f4bae6ec5686285ff83c8bddc2a3d9a7360c 100644 (file)
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -522,7 +522,7 @@ void radv_CmdUpdateBuffer(
 
                radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0));
                radeon_emit(cmd_buffer->cs, S_370_DST_SEL(mec ?
-                                               V_370_MEM_ASYNC : V_370_MEMORY_SYNC) |
+                                               V_370_MEM : V_370_MEM_GRBM) |
                                            S_370_WR_CONFIRM(1) |
                                            S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cmd_buffer->cs, va);

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 6daaed1223b0f8301f5377ca42ef86a5aa04dddb..0ddec4b6f4e64168025010a509863fc3b11b3c50 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1692,7 +1692,7 @@ void radv_CmdWriteTimestamp(
                        radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
                        radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
                                    COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
-                                   COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
+                                   COPY_DATA_DST_SEL(V_370_MEM));
                        radeon_emit(cs, 0);
                        radeon_emit(cs, 0);
                        radeon_emit(cs, query_va);

diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index b6920c95e34aad8b1fbc8223f72cc22be9ae0134..be394119af631a52a8f000e72ff77e6010038f0c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -266,7 +266,7 @@ static void si_fine_fence_set(struct si_context *ctx,
        if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
                struct radeon_cmdbuf *cs = ctx->gfx_cs;
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+               radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
                        S_370_WR_CONFIRM(1) |
                        S_370_ENGINE_SEL(V_370_PFP));
                radeon_emit(cs, fence_va);

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 6b89a1192d9edea775320b1e8bdbd14665b0ecbc..6ed45bb767e4da60fedd05d2393ccc385aa57767 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -528,7 +528,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
                /* Initialize the memory. */
                struct radeon_cmdbuf *cs = sctx->gfx_cs;
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
+               radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
                            S_370_WR_CONFIRM(1) |
                            S_370_ENGINE_SEL(V_370_ME));
                radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index dd670f3f670d4f1ced2bbb6bd6448b06e94cfc00..ea8c5d054b58bc5795271ba8359882ae1697d5a8 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1596,7 +1596,7 @@ void si_trace_emit(struct si_context *sctx)
        uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
+       radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) |
                    S_370_WR_CONFIRM(1) |
                    S_370_ENGINE_SEL(V_370_ME));
        radeon_emit(cs, va);