OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
- fd_event_write(ctx, ring, PERFCOUNTER_STOP);
+ fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP);
fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
- fd_event_write(ctx, ring, PERFCOUNTER_STOP);
+ fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP);
fd_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
int i = ffs(planes) - 1;
planes &= ~(1U << i);
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
}
if (dirty & FD_DIRTY_VIEWPORT) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
}
if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
if (dirty & FD_DIRTY_VERTTEX) {
if (vp->has_samp)
OUT_RING(ring, 0x00000000);
}
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
OUT_RING(ring, 0x00007fff);
OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
- fd3_emit_cache_flush(ctx, ring);
+ fd3_emit_cache_flush(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, 0x00000000);
- fd_event_write(ctx, ring, CACHE_FLUSH);
+ fd_event_write(batch, ring, CACHE_FLUSH);
if (is_a3xx_p0(ctx->screen)) {
OUT_PKT3(ring, CP_DRAW_INDX, 3);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
fd_hw_query_enable(batch, ring);
void fd3_emit_init(struct pipe_context *pctx);
static inline void
-fd3_emit_cache_flush(struct fd_context *ctx, struct fd_ringbuffer *ring)
+fd3_emit_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) |
A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0));
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
OUT_RING(ring, 2); /* NumIndices */
OUT_RING(ring, 2);
OUT_RING(ring, 1);
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS));
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1);
OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0));
OUT_RING(ring, fui(x1));
OUT_RING(ring, fui(y1));
- fd3_emit_cache_flush(ctx, ring);
+ fd3_emit_cache_flush(batch, ring);
for (i = 0; i < 4; i++) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) |
A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0));
if (ctx->screen->gpu_id == 320) {
emit_binning_workaround(batch);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
OUT_RING(ring, 0x00007fff);
}
/* emit IB to binning drawcmds: */
ctx->emit_ib(ring, batch->binning);
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
/* and then put stuff back the way it was: */
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w));
- fd_event_write(ctx, ring, CACHE_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, CACHE_FLUSH);
+ fd_wfi(batch, ring);
if (ctx->screen->gpu_id == 320) {
/* dummy-draw workaround: */
OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
OUT_RING(ring, 0); /* NumIndices */
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
}
OUT_PKT3(ring, CP_NOP, 4);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
if (ctx->screen->gpu_id == 320) {
emit_binning_workaround(batch);
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (ctx->needs_rb_fbd) {
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
assert(pipe->w * pipe->h);
- fd_event_write(ctx, ring, HLSQ_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, HLSQ_FLUSH);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
INDEX_SIZE_IGN, USE_VISIBILITY, 0));
OUT_RING(ring, 0); /* NumIndices */
- fd_event_write(batch->ctx, ring, ZPASS_DONE);
+ fd_event_write(batch, ring, ZPASS_DONE);
OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1);
OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);
struct fd_ringbuffer *ring = ctx->batch->draw;
if (ctx->rasterizer->rasterizer_discard) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT3(ring, CP_REG_RMW, 3);
OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
draw_impl(ctx, ctx->batch->draw, &emit);
if (ctx->rasterizer->rasterizer_discard) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT3(ring, CP_REG_RMW, 3);
OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
emit_marker(ring, 7);
- fd_reset_wfi(batch->ctx);
+ fd_reset_wfi(batch);
}
}
if (dirty & FD_DIRTY_VIEWPORT) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
/* emit IB to binning drawcmds: */
ctx->emit_ib(ring, batch->binning);
- fd_reset_wfi(ctx);
- fd_wfi(ctx, ring);
+ fd_reset_wfi(batch);
+ fd_wfi(batch, ring);
/* and then put stuff back the way it was: */
A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
- fd_event_write(ctx, ring, CACHE_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, CACHE_FLUSH);
+ fd_wfi(batch, ring);
}
/* before first tile */
}
if (ctx->needs_rb_fbd) {
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
assert(pipe->w * pipe->h);
- fd_event_write(ctx, ring, HLSQ_FLUSH);
- fd_wfi(ctx, ring);
+ fd_event_write(batch, ring, HLSQ_FLUSH);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
OUT_RING(ring, 1); /* NumInstances */
OUT_RING(ring, 0); /* NumIndices */
- fd_event_write(batch->ctx, ring, ZPASS_DONE);
+ fd_event_write(batch, ring, ZPASS_DONE);
return samp;
}
* just hard coded. If we start exposing more countables than we
* have counters, we will need to be more clever.
*/
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A4XX_CP_PERFCTR_CP_SEL_0, 1);
OUT_RING(ring, CP_ALWAYS_COUNT);
}
* shot, but that's really just polishing a turd..
*/
- fd_wfi(batch->ctx, ring);
+ fd_wfi(batch, ring);
/* copy sample counter _LO and _HI to scratch: */
OUT_PKT3(ring, CP_REG_TO_MEM, 2);
batch->num_draws = 0;
batch->stage = FD_STAGE_NULL;
+ fd_reset_wfi(batch);
+
/* reset maximal bounds: */
batch->max_scissor.minx = batch->max_scissor.miny = ~0;
batch->max_scissor.maxx = batch->max_scissor.maxy = 0;
bool blit : 1;
bool back_blit : 1; /* only blit so far is resource shadowing back-blit */
+ /* Keep track if WAIT_FOR_IDLE is needed for registers we need
+ * to update via RMW:
+ */
+ bool needs_wfi : 1;
+
/* To decide whether to render to system memory, keep track of the
* number of draws, and whether any of them require multisample,
* depth_test (or depth write), stencil_test, blending, and
*ptr = batch;
}
+static inline void
+fd_reset_wfi(struct fd_batch *batch)
+{
+ batch->needs_wfi = true;
+}
+
+/* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
+ * been one since last draw:
+ */
+static inline void
+fd_wfi(struct fd_batch *batch, struct fd_ringbuffer *ring)
+{
+ if (batch->needs_wfi) {
+ OUT_WFI(ring);
+ batch->needs_wfi = false;
+ }
+}
+
+/* emit a CP_EVENT_WRITE:
+ */
+static inline void
+fd_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
+ enum vgt_event_type evt)
+{
+ OUT_PKT3(ring, CP_EVENT_WRITE, 1);
+ OUT_RING(ring, evt);
+ fd_reset_wfi(batch);
+}
+
#endif /* FREEDRENO_BATCH_H_ */
util_queue_init(&ctx->flush_queue, "flush_queue", 16, 1);
}
- fd_reset_wfi(ctx);
-
util_slab_create(&ctx->transfer_pool, sizeof(struct fd_transfer),
16, UTIL_SLAB_SINGLETHREADED);
*/
bool in_blit : 1;
- /* Keep track if WAIT_FOR_IDLE is needed for registers we need
- * to update via RMW:
- */
- bool needs_wfi : 1;
-
/* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION? At least on a3xx
* it is not a banked context register, so it needs a WFI to update.
* Keep track if it has actually changed, to avoid unneeded WFI.
return (1 << prim) & ctx->primtype_mask;
}
-static inline void
-fd_reset_wfi(struct fd_context *ctx)
-{
- ctx->needs_wfi = true;
-}
-
-/* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
- * been one since last draw:
- */
-static inline void
-fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
-{
- if (ctx->needs_wfi) {
- OUT_WFI(ring);
- ctx->needs_wfi = false;
- }
-}
-
-/* emit a CP_EVENT_WRITE:
- */
-static inline void
-fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
- enum vgt_event_type evt)
-{
- OUT_PKT3(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, evt);
- fd_reset_wfi(ctx);
-}
-
struct pipe_context * fd_context_init(struct fd_context *ctx,
struct pipe_screen *pscreen, const uint8_t *primtypes,
void *priv);
emit_marker(ring, 7);
- fd_reset_wfi(batch->ctx);
+ fd_reset_wfi(batch);
}
/* emit IB to drawcmds: */
ctx->emit_ib(batch->gmem, batch->draw);
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
/* emit gmem2mem to transfer tile back to system memory: */
ctx->emit_tile_gmem2mem(batch, tile);
/* emit IB to drawcmds: */
ctx->emit_ib(batch->gmem, batch->draw);
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
}
void
}
}
- fd_reset_wfi(ctx);
+ fd_reset_wfi(batch);
ctx->stats.batch_total++;
}
fd_ringbuffer_flush(batch->gmem);
-
- fd_reset_wfi(ctx);
}
/* tile needs restore if it isn't completely contained within the
if (tile_stride == 0)
return;
- fd_wfi(batch->ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0 (ring, HW_QUERY_BASE_REG, 1);
OUT_RELOCW(ring, fd_resource(batch->query_buf)->bo, offset, 0, 0);
}
batch = fd_batch_from_fb(&ctx->screen->batch_cache, ctx, framebuffer);
fd_batch_reference(&ctx->batch, NULL);
+ fd_reset_wfi(batch);
ctx->batch = batch;
ctx->dirty = ~0;
size = MIN2(size, 4 * max_const);
if (size > 0) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, v->type, 0,
cb->buffer_offset, size,
cb->user_buffer, cb->buffer);
}
}
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
}
}
size *= 4;
if (size > 0) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, v->type, base,
0, size, v->immediates[0].val, NULL);
}
}
}
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
}
}
vertex_params_size = ARRAY_SIZE(vertex_params);
}
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
vertex_params_size, vertex_params, NULL);
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