};
surf->clear_color =
iris_resource_get_clear_color(res, NULL, NULL);
+ surf->clear_color_addr = (struct blorp_address) {
+ .buffer = res->aux.clear_color_bo,
+ .offset = res->aux.clear_color_offset,
+ .reloc_flags = 0,
+ .mocs = vtbl->mocs(res->aux.clear_color_bo),
+ };
}
// XXX: ASTC
color = convert_fast_clear_color(ice, res, color, swizzle);
- if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
+ bool color_changed = !!memcmp(&res->aux.clear_color, &color,
+ sizeof(color));
+
+ if (color_changed) {
/* We decided that we are going to fast clear, and the color is
* changing. But if we have a predicate bit set, the predication
* affects whether we should clear or not, and if we shouldn't, we
iris_resource_set_clear_color(ice, res, color);
- /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
- * is redundant and can be skipped.
+ /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
+ * changed, the clear is redundant and can be skipped.
*/
- if (aux_state == ISL_AUX_STATE_CLEAR)
+ if (!color_changed && aux_state == ISL_AUX_STATE_CLEAR)
return;
/* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
*/
iris_emit_end_of_pipe_sync(batch, PIPE_CONTROL_RENDER_TARGET_FLUSH);
+ /* If we reach this point, we need to fast clear to change the state to
+ * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
+ */
+ blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR;
+
struct blorp_batch blorp_batch;
blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
const struct gen_device_info *devinfo = &batch->screen->devinfo;
- enum blorp_batch_flags blorp_flags = BLORP_BATCH_NO_UPDATE_CLEAR_COLOR;
+ enum blorp_batch_flags blorp_flags = 0;
if (render_condition_enabled) {
if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
depth = p_res->format == PIPE_FORMAT_Z32_FLOAT ? depth :
(unsigned)(depth * depth_max) / (float)depth_max;
+ bool update_clear_depth = false;
+
/* If we're clearing to a new clear value, then we need to resolve any clear
* flags out of the HiZ buffer into the real depth buffer.
*/
* value so this shouldn't happen often.
*/
iris_hiz_exec(ice, batch, res, res_level, layer, 1,
- ISL_AUX_OP_FULL_RESOLVE);
+ ISL_AUX_OP_FULL_RESOLVE, false);
iris_resource_set_aux_state(ice, res, res_level, layer, 1,
ISL_AUX_STATE_RESOLVED);
}
}
const union isl_color_value clear_value = { .f32 = {depth, } };
iris_resource_set_clear_color(ice, res, clear_value);
+ update_clear_depth = true;
}
for (unsigned l = 0; l < box->depth; l++) {
iris_resource_get_aux_state(res, level, box->z + l);
if (aux_state != ISL_AUX_STATE_CLEAR) {
iris_hiz_exec(ice, batch, res, level,
- box->z + l, 1, ISL_AUX_OP_FAST_CLEAR);
+ box->z + l, 1, ISL_AUX_OP_FAST_CLEAR,
+ update_clear_depth);
}
}
struct iris_batch *batch,
struct iris_resource *res,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum isl_aux_op op)
+ unsigned int num_layers, enum isl_aux_op op,
+ bool update_clear_depth)
{
assert(iris_resource_level_has_hiz(res, level));
assert(op != ISL_AUX_OP_NONE);
ISL_AUX_USAGE_HIZ, level, true);
struct blorp_batch blorp_batch;
- blorp_batch_init(&ice->blorp, &blorp_batch, batch,
- BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
+ enum blorp_batch_flags flags = 0;
+ flags |= update_clear_depth ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR;
+ blorp_batch_init(&ice->blorp, &blorp_batch, batch, flags);
blorp_hiz_op(&blorp_batch, &surf, level, start_layer, num_layers, op);
blorp_batch_finish(&blorp_batch);
}
if (hiz_op != ISL_AUX_OP_NONE) {
- iris_hiz_exec(ice, batch, res, level, layer, 1, hiz_op);
+ iris_hiz_exec(ice, batch, res, level, layer, 1, hiz_op, false);
switch (hiz_op) {
case ISL_AUX_OP_FULL_RESOLVE:
{
if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
res->aux.clear_color = color;
- struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
- /* We can't update the clear color while the hardware is still using
- * the previous one for a resolve or sampling from it. Make sure that
- * there are no pending commands at this point.
- */
- /* TODO: Make these pipe controls gen-specific?
- *
- * We don't really need them on gen <= 9 where we are reading the
- * clear color from the surface state and clear_params, so they
- * shouldn't be needed. On gen11, the clear color is read from this
- * buffer, but the clear depth is still read from CLEAR_PARAMS, so we
- * could probably skip it in the HiZ case as well.
- *
- * Need to also check that for i965.
- */
- iris_emit_pipe_control_flush(batch, PIPE_CONTROL_CS_STALL);
- for (int i = 0; i < 4; i++) {
- ice->vtbl.store_data_imm32(batch, res->aux.clear_color_bo,
- res->aux.clear_color_offset + i * 4,
- color.u32[i]);
- }
- iris_emit_pipe_control_flush(batch,
- PIPE_CONTROL_STATE_CACHE_INVALIDATE);
return true;
}
struct iris_batch *batch,
struct iris_resource *res,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum isl_aux_op op);
+ unsigned int num_layers, enum isl_aux_op op,
+ bool update_clear_depth);
/**
* Prepare a miptree for access
projects / mesa.git / commitdiff