i965/gen8+: Remove redundant zeroing of surface state

The allocate_surface_state already zeroes out the surface state, and doing it
later in the function is destructive for what we want to accomplish when we
split out support for gen9 fast clears (next patch).

NOTE: Only dword 12 actually needed to be fixed, but it seemed more consistent
to remove the other instances as well. I can make an argument both ways (open
coding it, vs. not). I can rework the next patch if requires.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 18b86652fd2491a56d5f48f198a2ff12488005f1..eaaecd3df66548cb6a08ee5aa53ba27b614cd770 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -284,8 +284,6 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
                           GEN8_SURFACE_AUX_PITCH) |
                 aux_mode;
-   } else {
-      surf[6] = 0;
    }
 
    surf[7] = mt->fast_clear_color_value |
@@ -302,11 +300,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
                               aux_mt->bo, 0,
                               I915_GEM_DOMAIN_SAMPLER,
                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
-   } else {
-      surf[10] = 0;
-      surf[11] = 0;
    }
-   surf[12] = 0;
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->batch.bo,
@@ -514,8 +508,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
                 SET_FIELD((aux_mt->pitch / tile_w) - 1,
                           GEN8_SURFACE_AUX_PITCH) |
                 aux_mode;
-   } else {
-      surf[6] = 0;
    }
 
    surf[7] = mt->fast_clear_color_value |
@@ -533,11 +525,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
                               offset + 10 * 4,
                               aux_mt->bo, 0,
                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
-   } else {
-      surf[10] = 0;
-      surf[11] = 0;
    }
-   surf[12] = 0;
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
                            offset + 8 * 4,